A network accessible node that facilitates management of a fleet of portable communication devices (EIR terminal), including portable data terminals and/or barcode readers, by directing performance of software upgrade and/or configuration update actions by one or more members of the fleet of EIR terminals.

Data collection system having eir terminal interface node

Management of data communication between a peripheral device and host computer system is provided. A peripheral device exposes to a host computer system multiple interfaces for data communication between the peripheral device and the host computer system. The multiple interfaces are exposed over a single physical interface between the peripheral device and the host computer system, for communicating data between the peripheral device and multiple applications executing on the host computer system. The multiple interfaces can include a data collection interface facilitating collection of data from the peripheral device by an application of the multiple applications executing on the host computer system.

Managing data communication between a peripheral device and a host

Methods managing data communication between a peripheral device and host computer system are provided. A physical interface for communicating data between a peripheral device and the plurality of applications executing on the host computer system is opened and controlled by a software module. A first virtual interface and a second virtual interface of the software module are exposed to an operating system of the host computer system, and the operating system exposes the first virtual interface and the second virtual interface to the first application and the second application. The first virtual interface is used for communicating data between the peripheral device and the first application through the physical interface, and the second virtual interface is used for communicating data between the peripheral device and the second application through the physical interface.

Device management using virtual interfaces cross-reference to related applications

A network for remotely managing a plurality of remote devices that are each individually configurable to have selected operating characteristics includes a server connected to the network and to the plurality of remote devices, and a display coupled to a computer which is connected to the network. Also included are means for assigning a common icon to each remote device of the same type and displaying the icons on the server display, and means for coloring each icon to indicate a current configuration status of each remote device and for displaying the color on the icon on the display.

Remote device management interface

A single chip dual function 10 Base-T/100 Base-X physical layer interface device (PHY) compatible with existing 5 V parts is provided The PHY includes a media-independent interface (MII) and connects to an unshielded twisted pair cable via an isolation transformer and a single RJ45 connector The PHY includes built-in auto-negotiation circuitry that allows for automatic selection of half/full duplex 10 Base-T and 100 Base-TX, while auto-polarity correction circuitry ensures immunity to receive pair reversal in the 10 Base-T mode of operation The PHY includes internal PLL circuitry that uses a single 20 MHz clock or crystal, but that is suitable for either speed mode The PHY includes low-power and power down modes The 10 Base-T portions of the PHY include smart squelch for improved receive noise immunity The PHY includes high jitter tolerance clock recovery circuitry and transmit jabber detection circuitry The 10 Base-T portions of the PHY include on board transmit waveshaping The 100 Base-X portions of the PHY include synthesized rise time control for reduced electromagnetic interference (EMI) The PHY includes a programmable transmit voltage amplitude for 100 Base-X MLT-3 waveform generation and integrated adaptive equalization circuitry and baseline wander correction (DC restoration) circuitry for the 100 Base-X receiver

Physical layer interface device

A current amplifier driver capable of driving both 10 Base-T signalling and 100 Base signalling in a Local Area Network (LAN) includes one constant current source. A voltage controlled switch is contained in each of four vertical segment of an H-bridge circuit. Two voltage signals are applied to the switches to control the direction of current from a constant current source across a load. When one of the voltage signals is high, the other is low and two switches of the four switches turn on. The current amplifier driver sinks the constant current in a first direction, such that a voltage drop across the output nodes is positive. When the other voltage signal is high the switches that were on turn off, and the other two switches turn on to sink the constant current across the load in the opposite direction, such that a voltage drop across the output nodes is negative. When both voltage signals are low, all four switches turn off, and the output voltage is zero. In this manner, a differential signal is generated across a resistive load.

Fully switched, class-B, high speed current amplifier driver

An RC calibration circuit, which utilizes a resistor and a variable capacitor connected in parallel, reduces power consumption and increases the accuracy of the calibration by comparing the voltage on the resistor to the voltage on the capacitor after a predetermined time has expired since the capacitor began charging up. The result of the comparison, which indicates whether the voltage on the resistor is greater than the voltage on the capacitor, is then used to adjust the capacitance of the capacitor to servo the RC time constant to a predetermined value.

RC calibration circuit with reduced power consumption and increased accuracy

This paper describes a new topology and implementation of a 10-Gbits/s low-voltage differential-signaling (LVDS) voltage-mode output driver designed for high-speed data-transfer applications. Using a positive-feedback technique, the driver achieves ultralow-power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized, and good signal integrity is achieved. The driver, which consists of a predriver and an output stage, consumes a total of 15.63-mW at-speed power. In measurements, the driver, which was a part of an equalizer chip, achieved a peak-to-peak jitter of 11 ps at 10 Gbits/s and a return-loss performance of less than -15 dB. It provides a single-ended output swing of 400 mV and a common-mode voltage of 1.25 V, which are compliant with LVDS standards. The chip is fabricated in a standard 2.5-V/1.2-V SiGe BiCMOS technology with 100-GHz peak ft and is packaged in a commercial LLP package.

An Ultralow-Power 10-Gbits/s LVDS Output Driver

A calibration circuit adjusts a differential output voltage from a line driver circuit when the differential output voltage falls outside a specified tolerance range. The calibration circuit includes a sample and hold circuit which samples the differential output voltage and holds a representative signal. A comparator compares the held signal with a reference voltage signal. When the held signal is greater than the reference voltage signal the comparator outputs a LOW signal and when the held signal is less than the reference voltage signal the comparator outputs a HIGH signal. The comparator output signal is stored in a memory circuit of a control logic. The control logic instructs an up/down counter to increment when the comparator output is LOW and to decrement when the comparator output is HIGH. A calibration current source sinks a unit of calibration current when the comparator output is LOW and sources a unit of calibration current when the comparator output is HIGH. The calibration current is added to an input current to calibrate the differential output voltage towards the specified tolerance range. In a next cycle of the calibration sequence, if a new comparator output signal is different from that stored in the memory circuit, the calibration sequence ceases. However, if the new comparator output signal is the same as that stored in the memory circuit the calibration sequence continues.

Line driver calibration circuit

The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds the first support structure on the substrate. The first and second support structures are each configured to support an electrical connector to be formed over the first and second support structures on the substrate.

Electrical interconnect with minimal parasitic capacitance

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Jitendra Mohan

Author Tools

Chat about Author