Anti‐ambipolar heterojunctions are vital in constructing high‐frequency oscillators, fast switches, and multivalued logic (MVL) devices, which hold promising potential for next‐generation integrated circuit chips and telecommunication technologies. Thanks to the strategic material design and device integration, anti‐ambipolar heterojunctions have demonstrated unparalleled device and circuit performance that surpasses other semiconducting material systems. This review aims to provide a comprehensive summary of the achievements in the field of anti‐ambipolar heterojunctions. First, the fundamental operating mechanisms of anti‐ambipolar devices are discussed. After that, potential materials used in anti‐ambipolar devices are discussed with particular attention to 2D‐based, 1D‐based, and organic‐based heterojunctions. Next, the primary device applications employing anti‐ambipolar heterojunctions, including anti‐ambipolar transistors (AATs), photodetectors, frequency doublers, and synaptic devices, are summarized. Furthermore, alongside the advancements in individual devices, the practical integration of these devices at the circuit level, including topics such as MVL circuits, complex logic gates, and spiking neuron circuits, is also discussed. Lastly, the present key challenges and future research directions concerning anti‐ambipolar heterojunctions and their applications are also emphasized.

Anti-Ambipolar Heterojunctions: Materials, Devices, and Circuits.

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single-VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. 

https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2.12152

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

The history of ternary adders goes back to more than six decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This paper aims to conduct a survey to be familiar with the utilized design methodologies and logic families and their prevalence. Although the number of papers about this topic is high, almost none of the previously presented TFAs are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. Moreover, they could have been simplified even further by assuming a partial TFA where the voltage of the output carry is either 0V or VDD. This way, less static power would be dissipated. Therefore, a strong motivation is to correct and enhance the previous designs. Furthermore, different simulation setups, which are not realistic enough, have been taken into account. Therefore, the simulation results reported in the previous papers are neither comparable nor entirely valid. Among the 75 papers in which a new design of TFA has been given, 11 papers are selected, simplified, and simulated in this paper. Simulations are carried out by HSPICE and 32nm CNFET technology while considering a standard test-bed and a complete input pattern to reveal the maximum cell delay. The simplified partial TFAs outperform their original versions in delay, power, and transistor count.

Comprehensive Survey of Ternary Full Adders: Statistics, Corrections, and Assessments

The predicted end of scaling and the exponential increase of user data in the era of the connected world are asking whether the current binary systems in CMOS can successfully provide solutions to the expected challenges. Regarding these challenges, ternary systems are showing a high potential to provide solutions to these known issues. In detail, the tunnelling-based MOSFET (T-CMOS) is reported as promising compared to any other ternary devices studied. However, despite the potential, studies lack how a complete system can be designed in actual T-CMOS-based circuitry. Therefore, in this paper, we provide a holistic study of how T-CMOS-based circuits can be designed. In detail, 1) we provide a pathway to designing a balanced ternary full adder and provide the fundamental of how combinational ternary logic can be designed in T-CMOS. 2) We present various sequential ternary logic based on T-CMOS. 3) We present various circuit techniques that could enhance the performance of combinational and sequential ternary logic. Based on our study, we provide the first balanced ternary adder that the transistor count is only 42 and enhance the operating frequency of the T-CMOS-based ternary system by 5.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> to 58.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> .

Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design

This article proposes a novel dopingless ternary FET (DLT-FET) composed of the longitudinal metal-source/InAs-channel/InAs-drain structure for compact implementation of the ternary inverter. A single DLT-FET mixes two types of carrier transport mechanisms: 1) according to the concept of charge plasma, the Band-to-Band tunneling (BTBT) can occur at channel/drain interface by metal work function engineering; 2) Schottky Barrier tunneling (SBT) at the source/channel interface. The mechanism of the DLT-FET is verified with the help of TCAD tools. The simulation results revealed that both N/P-type DLT-FETs have a flat drain current characteristic around <italic>V</italic>G = 0.5<italic>V</italic>DD, where the <italic>V</italic>G-independent <italic>I</italic>BTBT dominates the drain current. The stable third output voltage can be obtained through the voltage dividing, while both the <italic>I</italic>SBT and <italic>I</italic>BTBT generate the other voltage levels of 0 V and 1.0<italic>V</italic>DD. Furthermore, the effects of a series of key device parameters on DLT-FETs and ternary inverter performance are evaluated. The ternary inverter can be implemented by simply replacing two transistors with N/P-type DLT-FETs in a conventional binary inverter and selecting appropriate device parameters for exhibiting comparable transfer characteristics.

A Novel Dopingless Ternary FET with the Metal Source for Ternary Inverter Implementation

As the development of binary systems forecasted to reach to its end, ternary system is gaining more attention. However, most ternary logic circuits were not considered to be a ‘true’ competitor to binary systems. To counter this common belief on ternary logic, in this study, we propose a ternary logic system based on depletion-mode MOSFETs and conventional MOSFETs that can truly compete with binary systems in terms of power and delay. Based on our novel circuitry of 11 logic gates, we illustrate that (1) our circuits consume near-zero static current on all logic states (−1, 0, +1), (2) our standard ternary inverter (STI) shows improved PDP of 71× and 245× compared to conventional CNTFET or memristor and MOSFET based ternary circuits, and (3) our balanced ternary full adder (BTFA) shows 48× improved power consumption compared to other ternary-device based adders and 5.3× improved power compared to the same devices. With our results, we highlight that ternary logic is now competitive to binary.

Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs

Ternary logic is said to become the potential solution to overcome the issues we encounter in binary systems. To enlighten this potential, we propose a ternary logic based on novel Anti-ambipolar transistors (AATs) and PMOSs. Conventional AATs require a complex fabrication process, and their operation is beyond the range of typical CMOS (>5 $V$). However, Inkjet-printed AATs are easy to fabricate, and their operating voltage is under 2V. Thus, Inkjet-based AATs are highly-suitable to use with other printable devices. Therefore, in this paper, we propose a set of novel ternary logic based on printed AATs and carbon-nanotube PMOSs. With these AATs and PMOSs, we propose 10 novel logic gates that include a practical balanced ternary full adder (TFA). Our TFA presents a compact design that can be implemented only with 41 PMOSs and 17 AATs. Our TFA reduces transistor count by −22.6% compared to the latest TFA design. We highlight that our ternary logic cells based on AATs and PMOSs are 1) the most compact design in terms of transistor count and 2) very convenient to fabricate.

A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes

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Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs

A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes