Jie Wang
Tsinghua University
7 Papers
4 Citations
Jie Wang is an academic researcher from Tsinghua University. The author has contributed to research in topics: Balun & Center frequency. The author has an hindex of 1, co-authored 5 publications.
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Papers
The Design of a Planar-Spiral Transformers Balun Used in RF/MW Based on 0.13 μm CMOS Process
Jie Wang,Wenjun Zhang,Zhiping Yu +2 more
- 18 Apr 2007
TL;DR: In this paper, the design of a broadband monolithic passive balun using planar-spiral transformers structure is described and the performance of the balun is simulated, and the results are: the single port power loss (port-to-port conversion loss) is less than 7 dB.
3
High-gain Broadband CMOS Distributed Power Amplifier for 5G Communications
Peipei Li,Jie Wang,Jie Cui +2 more
- 12 Aug 2022
TL;DR: In this paper , an analysis and design of an mm-wave wideband distributed power amplifier (PA) based on SMIC 40nm CMOS technology is presented, which combines the active power division and power combination networks, and achieves a simulated output 1dB compression point of 15.04dBm, peak power-added efficiency (PAE) of 6% and a saturated output power of 19.45 dBm at 24 GHz.
1
An analytical method for the calculation of self and mutual inductance on RF circuit
Ruinan Chang,Jie Wang,Wenjun Zhang,Zhiping Yu +3 more
- 01 Oct 2007
TL;DR: According to GMD (Geometric Mean Distance) method and thickness modification, a set of advanced analytical formula for both self and mutual inductance is presented and is more effective than method based on FEA and more precise than empirical formula and fitting data techniques.
1
The design of a new spiral inductor balun used in RF/MW based on 0.13μm CMOS process
Jie Wang,Wenjun Zhang,Ruinan Chang,Zhiping Yu +3 more
- 01 Oct 2007
TL;DR: In this paper, the design of a new broadband monolithic passive balun using planar-spiral inductor transformers structure is described, and the performance of the balun is simulated, and results are: the single port power loss is less than 6 dB.
A Broadband Monolithic Balun Based on 0.13/spl mu/m CMOS Process Using Planar-Spiral Transformers
Jie Wang,Wenjun Zhang,Zhiping Yu +2 more
- 01 Oct 2006
TL;DR: In this paper, the design of a broadband monolithic passive balun using planar-spiral transformers structure is described, and the amplitude and phase unbalance between two balanced ports are less than 3 dB and from 20 to 30 GHz for the same frequency range 10deg, respectively.