Jianmin Miao
Shanghai Jiao Tong University
396 Papers
2.1K Citations
Jianmin Miao is an academic researcher from Shanghai Jiao Tong University. The author has contributed to research in topics: Wafer & Silicon. The author has an hindex of 50, co-authored 396 publications. Previous affiliations of Jianmin Miao include University of Surrey & Agency for Science, Technology and Research.
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Papers
Thickness and dielectric constant of dead layer in Pt/(Ba0.7Sr0.3)TiO3/YBa2Cu3O7-x capacitor
Bin Chen,H. W. Yang,L. Zhao,Jianmin Miao,Bingshe Xu,Xianggang Qiu,B. R. Zhao,X. Y. Qi,Xiangfeng Duan +8 more
TL;DR: In this article, the dead-layer (DL) thickness and the DL dielectric constant were investigated for the series capacitor model and the results showed that the DL thickness and DL Dielectric constants were respectively estimated to be 28 nm and 426 nm.
Numerical and Experimental Investigation of Thermomechanical Deformation in High-Aspect-Ratio Electroplated Through-Silicon Vias
Pradeep Dixit,Pradeep Dixit,Sun Yaofeng,Jianmin Miao,John H. L. Pang,Ritwik Chatterjee,Rao Tummala +6 more
TL;DR: In this paper, a numerical and experimental analysis of thermomechanical deformation in high-aspect-ratio copper electroplated through-silicon vias (TSVs), which were fabricated by deep reactive ion etching, thermal oxidation, and bottom-up electroplating processes, is presented.
A miniaturized silicon-based ground Ring Guarded patch resonator and filter
TL;DR: In this article, a ground ring guided microstrip patch filter was developed on the silicon wafer using micromachined technology, which can be used to lower the operating frequency up to one-third as compared to the traditional patch resonator.
High Aspect Ratio Vertical Through-Vias for 3D MEMS Packaging Applications by Optimized Three-Step Deep RIE
TL;DR: In this article, the etching of high aspect ratio (HOR) interconnects was performed by a simple, three-step deep reactive ion etching (RIE) technique, where three different platen powers were used for different etching durations.
Local synthesis of aligned carbon nanotube bundle arrays by using integrated micro-heaters for interconnect applications
TL;DR: A rapid synthesis process for local growth of the aligned carbon nanotube (CNT) bundle arrays in a quartz tube operated at room temperature is reported, which could find potential applications in three-dimensional IC wafer-level packaging.