Jiangping Wu
Southeast University
8 Papers
9 Citations
Jiangping Wu is an academic researcher from Southeast University. The author has contributed to research in topics: Monte Carlo method & Process variation. The author has an hindex of 2, co-authored 8 publications.
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Papers
An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation
TL;DR: Experimental results show the proposed model is highly fitted with Monte Carlo results for stochastic delay modeling of generic logic gates in near/subthreshold regime with less than 8% and 6% error in delay variability and delay prediction, showing maximum accuracy improvement about 40 times compared to preproposal models.
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region
Peng Cao,Jiangping Wu,Zhiyuan Liu,Jingjing Guo,Jun Yang,Longxing Shi +5 more
- 13 May 2019
TL;DR: The statistical models for drain current and gate delay in low voltage region are established in analytical form based on the log-skew-normal (LSN) distribution via moment matching technique, and the probability distribution function (PDF) curves obtained are highly fitted with Monte Carlo simulation results in sub/near-threshold regions.
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Patent
Safety reconfigurable framework capable of resisting power dissipation attack
Cao Peng,Shen Ailin,Jiangping Wu,Yang Jun,Shi Longxing +4 more
- 26 Sep 2017
TL;DR: In this paper, a safety reconfigurable framework capable of resisting power dissipation attack is presented, which comprises a multichannel data selector, a secret share safety protection module and a data path dynamic reconfiguration safety protection.
2
Analytical Gate Delay Variation Model with Temperature Effects in Near-Threshold Region Based on Log-Skew-Normal Distribution
TL;DR: In this article, the authors proposed an analytical model for gate delay variation considering temperature effects in the near-threshold region, where the delay variation model is constructed based on the log-skew normal distribution by moment matching.
1
Patent
Block cipher algorithm-oriented reconfigurable S box, reconfigurable computing array and gate control method
Cao Peng,Jiangping Wu,Li Zhaoqi,Liu Bo,Yang Jun,Shi Longxing +5 more
- 18 Aug 2017
TL;DR: In this article, a block cipher algorithm-oriented reconfigurable S box is presented, in which a gate control switch circuit is added to the S box and used for controlling an enable signal of S box to be in a valid or invalid state so as to control whether the box is subjected to table lookup operation or not.
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