Coarse-grained reconfigurable arrays (CGRAs) belong to the family of configurable processing architectures that have recently attracted increasing interest for their adaptability and efficiency. Research on CGRA architectures and their associated CAD tools is typically conducted empirically, by modelling a CGRA fabric, mapping applications onto it, and then assessing performance, power, and/or area (PPA). In this paper, we describe an open-source framework for such CGRA research - CGRA-ME - CGRA modelling and exploration. We describe the recently released version 2.0 of CGRA - ME, which incorporates a new mapping approach, support for elastic CGRAs, floating point, predication, hybrid RISC-V+CGRA systems, and more.

CGRA-ME 2.0: A Research Framework for Next-Generation CGRA Architectures and CAD

Coarse-grained reconfigurable architecture (CGRA) is a promising programmable hardware with high power-efficiency and high performance. However, compiling and optimizing loops with irregular branches on CGRAs is a challenge to fulfill the performance potential. Existing predication techniques, such as partial predication (PP) and full predication (FP), conservatively implement software pipeline with a static initiation interval (II) obtained from the maximum graph, and thus only parts of the graph in each loop iteration will be actually executed, resulting in underexploited performance. To exploit more loop-level parallelism for irregular branches, this article proposes a novel dynamic-II pipeline (DIP) scheme, which realizes a pipeline with variable II by accommodating multiple iterations of short path in one static configuration. Since the DIP scheme is effective to only certain types of branches, this article designs a hybrid compilation framework integrating other complementary methods, which selects the appropriate method for source programs according to a proposed performance evaluation model. Experimental results show that: 1) the hybrid compilation framework can effectively extract branch features, correctly choose and implement corresponding branch processing methods within acceptable compile time and 2) as compared to PP and FP, DIP brings a significant total execution time (TET) reduction by 27.21% and 22.04% on average when the execution probability of a short branch is 50%. 

Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA

Compute-intensive applications such as AI, bioinformatics, data centers and IoT have become the hot topic of our time, and these emerging applications are becoming increasingly demanding in terms of the computing power of SDCs. To meet the demanding computing power requirements of these applications, the scale of programmable computing resources in SDCs has increased rapidly. Therefore, how to use these computing resources conveniently and efficiently has gradually become a key issue affecting the application of SDCs. With the advent of large-scale programmable computing resources and emerging applications, the cost of manual mapping has seriously affected the development efficiency of users. Therefore, it is urgent to develop an automated compilation system for SDCs. 

Compilation System

Coarse-Grained Reconfigurable Architecture (CGRA) is a promising hardware with high power efficiency, high performance and flexibility. Compiling loops with branch is a challenge to static-scheduling CGRA. Conventional mapping algorithms usually only consider coarse-grained operator placement and coarse-grained data routing. How to route fine-grained data in case of dealing with branches and other control flows is not considered. Existing CGRA architectures also have no components dedicated to fine-grained computing, storage, and routing. This paper proposes 1) a novel hybrid compiler framework including performance evaluation, the generation and optimization of data flow graphs (DFG), mapping optimization and configuration generation, which addresses control flow compilation, 2) a lightweight modification to CGRA architecture to support explicit control-flow routing and Boolean operations. Experimental results show that 1) the hybrid compiler framework can effectively extract features of branches and choose appropriate methods, 2) graph optimization and graph balance effectively reduce the size of the DFG, thereby reducing compilation time and power consumption.

Compiling Loops with Branches on Static-Scheduling CGRA

CGRA (Coarse-grained Reconfigurable Architecture) has been widely considered as one of the most promising computing architectures to exploit spatial parallelism. Compared with the typical general-purpose architectures which are instruction-driven, most of the state-of-art CGRAs are designed following the data-driven strategy, leading to difficulties while dealing with control-flow (nested if-then-else structures, NITE). Tackling with this problem, existing techniques such as partial predication and full predication introduce extra conditional move and select operations, while state-based full predication (SFP) introduces sleep and awake operations to correctly implement the basic function of NITE. Meanwhile, performance degradation is also incurred by these redundant operations. In this paper, a novel tag-based full predication (TFP) strategy is proposed, trying to eliminate redundant operations and thus accelerate NITE on CGRAs. The extra tag field is added to each instruction word to implement distributed nullification and parallel tag register (TReg) overwriting. Hardware support for TFP is present, and experimental validation is based on RTL-level simulation with manual mapping. Results show that our method achieves over 30% performance gain on average compared with SFP at the expense of around 5% additional power consumption and ignorable area overhead.

Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Jiang Sha

Author Tools

Chat about Author

Papers

Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method