Jerrold E. Buggert

TL;DR: The UIPP as mentioned in this paper is a microprocessor unit working in conjunction with a serial communications controller, random access memory and read only memory memories, a communications input/output (I/O) system, a multiple set of timer units and a priority interrupt controller.

TL;DR: In this paper, a master microprocessor commands three subordinate controllers to permit concurrent data transfers through a buffer memory in both the Read and the Write directions, and a dual channel control from the master microprocessors actuates a DMA switch so that data transfers to/from the tape units can be controlled by switching on alternate control lines which regulate the data transfer operations.

TL;DR: In this paper, a maintenance processor forms port of a computer net work wherein the processor (also designated as the User Interface Processor) operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirming integrity of the system and also for displaying data for locating any faults or problems in the network.

TL;DR: In this article, a master microprocessor commands three subordinate controllers to permit concurrent data transfers through a buffer memory in both the Read and the Write directions, and a dual channel control from the master microprocessors actuates a DMA switch so that data transfers to/from the tape units can be controlled by switching on alternate control lines which regulate the data transfer operations.