Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance. 

This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors.

* Comprehensive coverage of all modern architecture description languages... use the right ADL to design your processor to fit your application;
* Most up-to-date information available about each architecture description language from the developers...save time chasing down reliable documentation;
* Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing...fit the ADL to your design cycle;

Processor Description Languages

A debugging system is described wherein an outer Smalltalk running on a real machine interacts with a GEM5 simulation of an inner Smalltalk. An experimental embodiment is applied towards understanding the behavior of a target-agnostic JIT prototype.

Live Introspection of Target-Agnostic JIT in Simulation

The conventional inheritance concept adopted in the current Object Oriented Programming (OOP) was applied more than three decades ago. It is acting on "is-a" hierarchy model, and has some defects; while OOP is trying to be more close to the real life, it is still far from genetics principles. Adopted inheritance concept means that the child class can inherit, and get everything that is public in the parent class automatically. This process has solved many problems, but it does not simulate what is really happening in our life, where each object can gain just the needed properties from the parent class. So, in simple words, conventional inheritance is not selective and is generating identical objects. One of introduced solutions was the selective inheritance. But, while conventional inheritance acts on “is-a” hierarchy model, the works that introduced the selective inheritance were also done on this model and still suffers from some problems. The inspiration from the “real life” genetics has led us to a selective inheritance acting upon a “Composed by” model rather than the “is-a” model, where the properties are classified into several classes according to "Composed by" relation. This paper proposes a Genetic approach to a new model for selective inheritance that is replacing the “is-a” hierarchy model by a “Composed by” one, which reduces the complexity and makes each object has its own definition. After that, it proposes a language extension to be adopted in any object oriented programming language.

http://www.sersc.org/journals/IJSEIA/vol8_no1_2014/6.pdf

A Bio-Inspired Approach to Selective Inheritance Modeling

Compiler Backend Generation from Structural Processor Models

Mower is a micro-architecture technique which targets the branch misprediction penalty in superscalar processors. It speeds-up the misprediction recovery process by dynamically evicting stale instructions and correcting the Register Alias Table (RAT) using explicit control dependency tracking. Tracking control dependencies is accomplished by using simple bit matrices. This low-overhead technique allows overlapping of the recovery process with instruction fetching, renaming and scheduling from the correct path. Our evaluation of the mechanism indicates that it yields performance very close to ideal recovery and provides up to 5% speed-up and 2% reduction in power consumption compared to a recovery mechanism using a reorder buffer and a walker. The simplicity of the mechanism should permit easy implementation of Mower in an actual processor.

/pdf/mower-a-new-design-for-non-blocking-misprediction-recovery-5bd507rgti.pdf

Mower: A New Design for Non-blocking Misprediction Recovery

Designing, testing, and producing a new computer processor is a complex and very expensive process. To reduce costly mistakes in hardware, the microarchitecture is usually designed and tested with the aid of a software simulator. The FAST System enables microarchitects to develop architecture simulators rapidly and is less error-prone than using a high level language such as C. In this paper, we describe how the FAST System's Architecture Description Language (ADL) has been extended to facilitate the description of complex instruction sets such as Intel's IA-32 instruction set architecture. In this respect, we demonstrate that the notion of inheritence, a key concept in object oriented programming languages can be extended for selective inheritence to enable the specification of complex instruction set architectures in architecture description languages.

/pdf/specification-of-intel-ia-32-using-an-architecture-2l8m6bkfgr.pdf

Specification of Intel IA-32 Using an Architecture Description Language

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Specification of Intel IA-32 Using an Architecture Description Language