Design and performance analysis of reconfigurable modified Vedic multiplier with 3-1-1-2 compressor

In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduces a novel lookup table based threshold attenuation technique, called threshold attenuated MSA (TAMSA). The proposed TAMSA implementation is shown to improve bit error rate (BER) performance compared to the conventional AMSA and MSA. Furthermore, a layered version of the TAMSA implementation is investigated to reduce hardware cost. Utilizing circuit optimization techniques, including a parallel computing structure, the proposed layered TAMSA field-programmable gate array (FPGA) implementation results show that the modified architecture requires no extra circuit power or circuit area compared to conventional AMSA, and only 0.07% extra leaf cells compared to conventional MSA.

Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders

This paper presents an efficient conflict-free memory address scheme for arbitrary 2k-point memory-based FFT processors. The address scheme can support in-place strategy, continuous-flow mode, and variable size for arbitrary long sized FFT. More over, the address scheme can adjust the throughput by changing the computation radix and the parallelism of the arithmetic processing units according to the specific implementation requirements. We have designed a configurable 128 — 2048 point FFT processor for LTE system. From the results, we can see the proposed address scheme has excellent point flexibility, hardware efficiency, and can support almost any 2k-point FFT implementations.

A generalized conflict-free address scheme for arbitrary 2k-point memory-based FFT processors

. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

/pdf/a-high-throughput-architecture-for-a-low-complexity-soft-3zroy5fyui.pdf

A high throughput architecture for a low complexity soft-output demapping algorithm

/pdf/digital-signal-processing-for-optical-coherent-communication-28er5p41xk.pdf

Digital Signal Processing for Optical Coherent Communication Systems

This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support 128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages.

Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors

This paper proposes a high speed and low complexity carrier recovery for 10Gb/s dual-polarization quadrature phase shift keying (DP-QPSK). The Viterbi and Viterbi (V&V) algorithm is commonly used as a typical method for phase noise recovery. The V&V algorithm performs data dependency elimination by using complex multipliers that raise the value of the M-ary PSK signal to the power of M. However, the V&V algorithm may not be suitable for extremely high-speed carrier recovery because of the complicated complex multipliers. To achieve high speed and low complexity, we propose a new algorithm which performs data dependency elimination without using the complex multipliers. As a result, the proposed algorithm has lower hardware complexity and a higher clock rate compared with the V&V algorithm.

High-speed and low complexity carrier recovery for DP-QPSK transmission

Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard

In this paper, we propose an enhanced eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for high-speed orthogonal frequency-division multiplexing (OFDM) systems to reduce the number of complex multipliers. The proposed processor can achieve a high throughput rate by using an eight-parallel data-path scheme and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the total number of complex multipliers by about 41%. The proposed eight-parallel FFT/IFFT processor has been designed and implemented with the 90 nm CMOS technology. It can reduce the gate count up to 16% and provide a throughput rate of up to 27.5 Gsamples/s.

Low complexity FFT/IFFT processor for high-speed OFDM system using efficient multiplier scheduling

This paper presents an efficient synchronizer architecture using the common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the satisfactory performance under worst channel condition and the efficient H/W resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&S™ SFU broadcast test equipment.

Efficient synchronizer architecture using common autocorrelator for DVB-S2

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