Jay Schleicher
Altera
9 Papers
114 Citations
Jay Schleicher is an academic researcher from Altera. The author has contributed to research in topics: Field-programmable gate array & Programmable logic device. The author has an hindex of 8, co-authored 9 publications.
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Papers
The Stratix II logic and routing architecture
David Lewis,Elias Ahmed,Gregg William Baeckler,Vaughn Betz,Mark Bourgeault,David Cashman,David Galloway,Michael D. Hutton,Christopher F. Lane,Andy L. Lee,Paul Leventis,Sandy Marquardt,Cameron McClintock,Ketan Padalia,Bruce B. Pedersen,Giles Powell,Boris Ratchev,Srinivas T. Reddy,Jay Schleicher,Kevin Stevens,Richard Yuan,Richard G. Cliff,Jonathan Rose +22 more
- 20 Feb 2005
TL;DR: This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows.
A Methodology for FPGA to Structured-ASIC Synthesis and Verification
Michael D. Hutton,Richard Yuan,Jay Schleicher,Gregg William Baeckler,Sammy Cheung,Kar Keng Chua,Hee Kong Phoon +6 more
- 06 Mar 2006
TL;DR: This paper addresses the verification issue with a methodology and fabric to directly tie FPGA prototype and functional in-system verification with a clean migration path to structured ASIC.
Improving FPGA Performance and Area Using an Adaptive Logic Module
Michael D. Hutton,Jay Schleicher,David Lewis,Bruce B. Pedersen,Richard Yuan,Sinan Kaptanoglu,Gregg William Baeckler,Boris Ratchev,Ketan Padalia,Mark Bourgeault,Andy L. Lee,Henry Kim,Rahul Saini +12 more
- 30 Aug 2004
TL;DR: A new adaptable FPGA logic element based on fracturable 6-LUTs is proposed, which fundamentally alters the longstanding belief that a 4-Lut is the most efficient area/delay tradeoff.
•Journal Article
Improving FPGA performance and area using an adaptive logic module
Michael D. Hutton,Jay Schleicher,David Lewis,Bruce B. Pedersen,Richard Yuan,Sinan Kaptanoglu,Gregg William Baeckler,Boris Ratchev,Ketan Padalia,Mark Bourgeault,Andy L. Lee,Henry Kim,Rahul Saini +12 more
TL;DR: In this paper, a new adaptable FPGA logic element based on fracturable 6-LUTs has been proposed, which fundamentally alters the longstanding belief that a 4LUT is the most efficient area/delay tradeoff.
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Interconnect enhancements for a high-speed PLD architecture
Michael D. Hutton,Vinson Chan,Peter J. Kazarian,Victor Maruri,Tony Ngai,Jim Park,Rakesh H. Patel,Bruce B. Pedersen,Jay Schleicher,Sergey Shumarayev +9 more
- 24 Feb 2002
TL;DR: This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications, and will present significant portions of the background research that contributed to the architectural decisions.