Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Hardware debugging in a hardware description language

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

In a multinode data processing system in which nodes exchange information over a network or through a switch, the mechanism which enables out-of-order data transfer via Remote Direct Memory Access (RDMA) also provides a corresponding ability to carry out broadcast operations, multicast operations, third party operations and conditional RDMA operations. In a broadcast operation a source node transfers data packets in RDMA fashion to a plurality of destination nodes. Multicast operation works similarly except that distribution is selective. In third party operations a single central node in a cluster or network manages the transfer of data in RDMA fashion between other nodes or creates a mechanism for allowing a directed distribution of data between nodes. In conditional operation mode the transfer of data is conditioned upon one or more events occurring in either the source node or in the destination node.

Third party, broadcast, multicast and conditional RDMA operations

Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is re-performed. If the trial does not converge on the decoded correct codeword (DCCW), then other trials are performed until either (i) the decoder converges on the DCCW or (ii) all permitted combinations of SBNs are exhausted. The starting state of a particular trial, and the set of SBNs available to that trial may change depending on the results of previous trials.

Error-floor mitigation of LDPC codes using targeted bit adjustments

Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Method and system for debugging an electronic system

A method and structure facilitates the debugging and test coverage capabilities of a microprocessor. A microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST) engines is disclosed. The debug block is capable of driving control information out onto a state machine output bus in response to an event and the control information can be selectively used to control signature analysis or recording elements of the microprcessor, such as multiple-input-shift-registers and first-in-first-out devices, that facilitate in the monitoring and debugging of the microprocessor. The signature and recording elements may or may not be contained within the one or more BIST engines and may or may not be used in conjunction with the memory arrays or BIST engine(s) of the microprocessor.

Method and system for flexible control of BIST registers based upon on-chip events

A method and apparatus for locating defects in an on-chip memory of an integrated circuit is presented. During a memory test of on-chip memory, a known data value is written to a word in the on-chip memory, and an output data value is read back from the same addressed word in memory. A comparison of the output data value and expected data value is performed within the integrated circuit, producing a comparison result indicating which of the bit cells in the addressed word have failed. The address and comparison result are transferred external to said integrated circuit and correspond to a bitmap entry in a bitmap. The execution of a full memory test results in a complete bitmap indicating all the failed cells of the on-chip memory.

On-the-fly memory testing and automatic generation of bitmaps

A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

Flexible and programmable BIST engine for on-chip memory array testing and characterization

A system and method are disclosed which provide the capability of repairing an optimum number of defective memory segments, such as RAM segments, in order to minimize the amount of unused repairing circuitry, such as fuses used for repairing defects within the memory. A preferred embodiment of the present invention provides a RAM block implemented such that the number of fuses required for repairing defects therein is proportional to the optimum number of defective segments capable of being repaired. A preferred embodiment allows for repairing an optimum number of defective segments, while being capable of repairing any of the segments (up to the optimum number) by mapping repair data to an appropriate defective segment. A preferred embodiment provides a repairable RAM block comprising multiple segments of RAM memory cells that are each repairable, a state machine capable of generating repair data for repairing one or more defective segments, a scan address machine capable of generating data identifying one or more defective segments, and a mapping circuitry for mapping the generated repair data of the state machine to the one or more defective segments specified by the scan address machine. Accordingly, by providing the capability of mapping generated repair data to any one of the segments of RAM that is detected as being defective, a preferred embodiment enables repairing an optimum number of defective segments, without being required to provide sufficient circuitry for repairing every segment of RAM.

Redundancy programming using addressable scan paths to reduce the number of required fuses

A novel method and apparatus for automatically programming a redundancy map for a circuit is presented. A circuit comprising a plurality of identical reconfigurable circuit elements and a redundant circuit element includes a redundancy map register which may be programmed to allow faulty circuit elements to be deactivated and bypassed and the redundant circuit element to be activated. A fault detector tests the circuit to generate a fault indicator indicating which one of the reconfigurable circuit elements is a faulty circuit element. An encoder encodes the fault indicator into an encoded fault indicator. A decoder decodes the encoded fault indicator to generate a redundancy map for configuring the reconfigurable circuit elements.

Method for automatically programming a redundancy map for a redundant circuit

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