A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Method and apparatus for performing multiply-add operations on packed data

In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads The processor also includes detection circuitry to detect speculation errors in the execution of the threads In another embodiment, the processor includes thread management logic to control dynamic creation of threads from a program

Processor having multiple program counters and trace buffers outside an execution pipeline

A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.

Executing partial-width packed data instructions

In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.

Multithreading processor with thread predictor

An apparatus for self-timed algorithmic execution comprises a functional logic set, a reference clock input and a pulse sequencer. The functional logic set receives input data in synchrony with a reference pulse set received at the reference clock input; performs algorithmic computations on the input data at a maximal-rate set by the pulse sequencer in accordance with the physical characteristics of the functional logic; generates output data; and transmits the output data in synchrony with the reference pulse set. The maximal-rate set by the pulse sequencer is independent of the reference pulse set. A method for self-timed algorithmic execution comprises the steps of: transferring input data to a functional logic set in synchrony with a reference clock; generating a maximal-rate pulse sequence, for driving the functional logic set at a rate dependent upon an algorithm execution time for the functional logic set but independent of the reference clock; generating output data from the functional logic set in response to the maximal-rate pulse sequence; and transferring the output data from the functional logic in synchrony with the reference clock.

Apparatus and method for self-timed algorithmic execution

In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.

Floating point processor with internal free-running clock

In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups The corresponding partial product terms are reduced in a regular array of small carry-save adder cells Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results

Method and apparatus for implementing binary multiplication using booth type multiplication

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Floating point processor with internal free-running clock

Method and apparatus for implementing binary multiplication using booth type multiplication