Energy-proportional designs would enable large energy savings in servers, potentially doubling their efficiency in real-life use. Achieving energy proportionality will require significant improvements in the energy usage profile of every system component, particularly the memory and disk subsystems.

/pdf/the-case-for-energy-proportional-computing-4un8a5n8c1.pdf

The Case for Energy-Proportional Computing

A system and method for recognizing data access patterns in large data sets and for preloading a cache based on the recognized patterns is provided. In some embodiments, the method includes receiving a data transaction directed to an address space and recording the data transaction in a first set of counters and in a second set of counters. The first set of counters divides the address space into address ranges of a first size, whereas the second set of counters divides the address space into address ranges of a second size that is different from the first size. One of a storage device or a cache thereof is selected to service the data transaction based on the first set of counters, and data is preloaded into the cache based on the second set of counters.

Cache optimization technique for large working data sets

A system, method, and medium for dynamically scaling the size of a fingerprint index in a deduplication storage system. Fingerprints are stored as entries in a fingerprint index, and the fingerprint index is scaled to fit into an in-memory cache to enable fast accesses to the index. A persistent copy of the full fingerprint index is stored on a non-volatile memory. The cached fingerprint index uses binary sampling to categorize half of the fingerprint entries as samples and protected, and the other half of the entries as non-samples and replaceable. When a search of the cached index results in a hit on a sample entry, all of the non-sample entries associated with the same container are copied from the persistent index to the cached index.

Method and system of deduplication-based fingerprint index caching

Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration

Versatile lane configuration using a pcie pie-8 interface

Techniques are described for allocating computing resources to a task from a shared hardware structure. The techniques may involve receiving a request to execute a task for a tenant on shared hardware resources, and determining a set of computing resources for allocation to the task based on a service level agreement associated with the tenant. The set of computing resources can be allocated to the task based on the service level agreement associated with the tenant. In some aspects, one or more performance counters associated with one or more of the computing resources can be monitored to determine an activity level for the one or more computing resources during execution of the task, and one or more allocations of the computing resources for execution of the task can be adjusted based on the activity level for the one or more computing resources.

Allocating processor resources based on a service-level agreement

In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

Cache implementing multiple replacement policies

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Combined Transparent/Non-Transparent Cache

In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Block-based non-transparent cache

In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

Managed credit update

Methods and apparatuses for utilizing a cache hint mechanism in which a requesting agent can provide hints as to how data corresponding to a request should be cached in a system cache within a memory controller. The way the system cache responds to received requests is determined by the cache hint provided by the originating requesting agent. When a request is accompanied by a de-allocate cache hint, the system cache causes a cache line hit by the request to be de-allocated. For a request with a do not allocate cache hint, the system cache does not allocate a cache line if the request misses in the system cache, and the system cache maintains a given cache line in its current state if the requests hits the given cache line.

System cache with cache hint control

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