James E. Smith

TL;DR: In this paper, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode, and the transition between the two modes using information that can be stored in one or more storages of the processor and elsewhere in a system.

TL;DR: In this article, a method for concurrent fault cross-checking in a computer having a plurality of simultaneous multithreading (SMT) processors, where each SMT processor simultaneously processes multiple threads, is presented.

TL;DR: The TNNs considered here employ online localized learning via spike timing dependency (STDP) to support continual, adaptive online learning, which contrasts with a large fraction of proposedTNNs that rely on compute-intensive back propagation learning methods, adapted, transferred, or inspired by conventional artificial neural networks (ANNs).

TL;DR: In this article, a system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode, resulting in generation and storage of auxiliary microcode.