The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units The fetch unit generally maintains a predetermined number of instructions in an instruction buffer The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent

High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution

A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Method and apparatus for interfacing a processor to a coprocessor

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

System and method for conditionally moving an operand from a source register to a destination register

Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage

Methods and apparatuses for managing load-store dependencies in an out-of-order processor. A load store dependency predictor may include a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes a counter to indicate a strength of the dependency prediction. If the counter is above a threshold, a dependency is enforced for the load-store pair. If the counter is below the threshold, the dependency is not enforced for the load-store pair. When a store is dispatched, the table is searched, and any matching entries in the table are armed. If a load is dispatched, matches on an armed entry, and the counter is above the threshold, then the load will wait to issue until the corresponding store issues.

Load-store dependency predictor content management

An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.

Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle

An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations The classifications associated with the instructions occur in the order in which the instructions occur in the sequence

CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle

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Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle

CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle