Algorithms for Memory Hierarchies

Frigo, Leiserson, Prokop and Ramachandran in 1999 introduced the ideal-cache model as a formal model of computation for developing algorithms in environments with multiple levels of caching, and coined the terminology of cache-oblivious algorithms. Cache-oblivious algorithms are described as standard RAM algorithms with only one memory level, i.e. without any knowledge about memory hierarchies, but are analyzed in the two-level I/O model of Aggarwal and Vitter for an arbitrary memory and block size and an optimal off-line cache replacement strategy. The result are algorithms that automatically apply to multi-level memory hierarchies. This paper gives an overview of the results achieved on cache-oblivious algorithms and data structures since the seminal paper by Frigo et al.

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Cache-oblivious algorithms and data structures

We propose a blocked version of Floyd's all-pairs shortest-paths algorithm The blocked algorithm makes better utilization of cache than does Floyd's original algorithm Experiments indicate that the blocked algorithm delivers a speedup (relative to the unblocked Floyd's algorithm) between 16 and 19 on a Sun Ultra Enterprise 4000/5000 for graphs that have between 480 and 3200 vertices The measured speedup on an SGI O2 for graphs with between 240 and 1200 vertices is between 16 and 2

/pdf/a-blocked-all-pairs-shortest-paths-algorithm-4hhonayaj1.pdf

A blocked all-pairs shortest-paths algorithm

We describe a model that enables us to analyze the running time of an algorithm in a computer with a memory hierarchy with limited associativity, in terms of various cache parameters. Our model, an extension of Aggarwal and Vitter's I/O model, enables us to establish useful relationships between the cache complexity and the I/O complexity of computations. As a corollary, we obtain cache-optimal algorithms for some fundamental problems like sorting, FFT, and an important subclass of permutations in the single-level cache model. We also show that ignoring associativity concerns could lead to inferior performance, by analyzing the average-case cache behavior of mergesort. We further extend our model to multiple levels of cache with limited associativity and present optimal algorithms for matrix transpose and sorting. Our techniques may be used for systematic exploitation of the memory hierarchy starting from the algorithm design stage, and dealing with the hitherto unresolved problem of limited associativity.

Towards a Theory of Cache-Efficient Algorithms

Due to the increasing gap between CPU and memory speed, cache performance plays an increasingly critical role in determining the overall performance of microprocessor systems. One of the important factors that a affect cache performance is the cache replacement policy. Despite the importance, current analytical cache performance models ignore the impact of cache replacement policies on cache performance. To the best of our knowledge, this paper is the first to propose an analytical model which predicts the performance of cache replacement policies. The input to our model is a simple circular sequence profiling of each application, which requires very little storage overhead. The output of the model is the predicted miss rates of an application under different replacement policies. The model is based on probability theory and utilizes Markov processes to compute each cache access' miss probability. The model realistic assumptions and relies solely on the statistical properties of the application, without relying on heuristics or rules of thumbs. The model's run time is less than 0.1 seconds, much lower than that of trace simulations. We validate the model by comparing the predicted miss rates of seventeen Spec2000 and NAS benchmark applications against miss rates obtained by detailed execution-driven simulations, across a range of different cache sizes, associativities, and four replacement policies, and show that the model is very accurate. The model's average prediction error is 1.41%,and there are only 14 out of 952 validation points in which the prediction errors are larger than 10%.

An analytical model for cache replacement policy performance

analyze them This paper describes a model for studying the cache performance of algorithms in a direct-mapped cache Using this model, we analyze the cache performance of several commonly occurring memory access patterns: (i) sequential and random memory traversals, (ii) systems of random accesses, and (iii) combinations of each For each of these, we give exact expressions for the number of cache misses per memory access in our model We illustrate the application of these analyses by determining the cache performance of two algorithms: the traversal of a binary search tree and the counting of items in a large array Trace driven cache simulations validate that our analyses accurately predict cache performance The key application of cache performance analysis is towards the cache conscious design of data structures and algorithms In our previous work we studied the cache conscious design of priority queues [13] and sorting algorithms [14], and were able to make significant performance improvements over traditional implementations by considering cache effects

Cache performance analysis of traversals and random accesses

How effectively a program uses the memory hierarchy of a computer system can have a tremendous impact on its performance. The failure of a program to access data in the cache memory, hence the need to access that data in main memory, has a cost of up to 100 cycles on today's systems, a penalty that is expected to rise with future systems. As a result much recent algorithm design research has been conscious of the cache, and has focused on its effective use. Understanding the behavior of the cache when developing algorithms is crucial to such research. 
We develop the cache performance analysis of algorithms whose primary goal is to determine the number of cache hits and cache misses that an algorithm incurs. We view an algorithm as a combination of basic memory access patterns, analyze each pattern's cache performance, and apply the analysis to accurately predict the cache performance of the algorithm. Our analysis is precise: we pay attention to constant factors and quantify performance for even moderate data sizes. Our caching model is realistic: we determine the performance of our access pattern models for direct-mapped caches and caches with a limited degree of set-associativity. For certain patterns that arise in accessing common data structures, we demonstrate and prove that set-associativity yields little or no benefit over direct-mapped caching.

Cache performance analysis of algorithms

We propose a method for constructing a tiling between a pair of planar polygons. Our technique uses multiresolution: tilings of lower resolution polygons are used to construct a tiling for the full resolution polygons. The tilings are constructed using banded refinement , by restricted dynamic programming, in roughly linear time and space. By contrast, the optimal dynamic programming method requires quadratic time and space. In our empirical study of surface reconstruction of brain contours our algorithm exhibited significant speedup over the optimal dynamic program, yet nearly always found an optimal reconstruction. Our approach appears to be generalizable to other geometric problems solvable by dynamic programming, and flexible enough to be tuned for varying data set characteristics.

Multiresolution banded refinement to accelerate surface reconstruction from polygons

The problem of sorting on a one-dimensional sub-bus array of processors is addressed. A one-dimensional sub-bus array has a bus connecting the processors which can be segmented into sub-buses on which an active processor can broadcast. The sub-bus broadcast capability is implemented on the MasPar MP-1 and MP-2 parallel computers. The sub-bus broadcast operation makes possible a new class of parallel sorting algorithms which can be characterized by parallel insertion steps. We restrict our attention to the class of sorting methods where parallel insertion steps are in the same direction, say left. For this class of one-way sorting strategies we prove a lower bound and give two strategies, the left greedy sort and the left adaptive insertion sort, both of which achieve the lower bound. Because our parallel insertion model is quite general, it is not necessarily the case that a sorting strategy in the model can be e ciently implemented on a real sub-bus array of processors. The left greedy sort cannot be e ciently implemented, but the left adaptive insertion sort can be e ciently implemented. The two sorting strategies have di erent properties and each is interesting in its own right.

Optimal one-way sorting on a one-dimensional sub-bus array

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Papers

Cache performance analysis of traversals and random accesses

Cache performance analysis of algorithms

Multiresolution banded refinement to accelerate surface reconstruction from polygons

Optimal one-way sorting on a one-dimensional sub-bus array

Multiresolution banded refinement to accelerate surface reconstruction from polygons