The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

How can neural networks learn the rich internal representations required for difficult tasks such as recognizing objects or understanding language?

https://dl.acm.org/doi/pdf/10.1145/3448250

Deep learning for AI

Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.

/pdf/piperench-a-co-processor-for-streaming-multimedia-2zu0mowwqv.pdf

PipeRench: a co/processor for streaming multimedia acceleration

PHiPAC was an early attempt to improve software performance by searching in a large design space of possible implementations to find the best one. At the time, in the early 1990s, the most efficient numerical linear algebra libraries were carefully hand tuned for specific microarchitectures and compilers, and were often written in assembly language. This allowed very precise tuning of an algorithm to the specifics of a current platform, and provided great opportunity for high efficiency. The prevailing thought at the time was that such an approach was necessary to produce near-peak performance. On the other hand, this approach was brittle, and required great human effort to try each code variant, and so only a tiny subset of the possible code design points could be explored. Worse, given the combined complexities of the compiler and microarchitecture, it was difficult to predict which code variants would be worth the implementation effort. PHiPAC circumvented this effort by using code generators that could easily generate a vast assortment of very different points within a design space, and even across very different design spaces altogether. By following a set of carefully crafted coding guidelines, the generated code was reasonably efficient for any point in the design space. To search the design space, PHiPAC took a rather naive but effective approach. Due to the human-designed and deterministic nature of computing systems, one might reasonably think that smart modeling of the microprocessor and compiler would be sufficient to predict, without performing any timing, the optimal point for a given algorithm. But the combination of an optimizing compiler and a dynamically scheduled mi-

Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology

Form of Control Expression % Abstract Form of Control Expression % others 32.4 ! function-call 3.8 object 15.5 object < integer-constant 2.2 object == object 8.9 object > integer-constant 1.8 ! object 7.4 function-call == object 1.6 function-call 7.4 object > object 1.4 expression 5.7 object != integer-constant 1.3 object != object 4.2 function-call == integer-constant 1.2 object == integer-constant 4.0 object < object 1.1 January 30, 2008 v 1.1 15 6.8.4 Selection statements 1740 selection-statements Fu nc tio n de fin iti on s 1 10 100 1,000 10,000 0 25 50 75 100 × × if • • else switch × × ××××××××××××××××××××××××××××××× ×××××× × ××× × ××××× ×× ×××× × ×× × × × × × × ××× × × ××× ×× × ××× × × × ××× × ×

The New C Standard (Excerpted material) An Economic and Cultural Commentary

The Spert-II fixed point vector microprocessor system performs training and recall faster than commercial workstations for neural networks used in speech recognition research. We have packaged a prototype full custom vector microprocessor, TO, as the Spert-II (Synthetic Perceptron Testbed II) workstation accelerator system. We originally developed Spert-II to accelerate multiparameter neural network training for speech recognition research. Our speech research algorithms constantly change. Also, neural nets are often integrated with other tasks to form complete applications. We thus desired a general purpose, easily programmable accelerator that could speed up a range of tasks.

/pdf/spert-ii-a-vector-microprocessor-system-2ydsjja8ok.pdf

Spert-II: a vector microprocessor system

The Ring Array Processor: a multiprocessing peripheral for connectionist applications

The authors have designed and implemented a ring array processor, RAP, for fast implementation of layered neural network algorithms. The RAP is a multi-DSP system targeted at continuous speech recognition using connectionist algorithms. Four boards, each with four Texas Instruments, TMS 320C30 DSPs, serve as an array processor for a 68020-based host running a real-time operating system. The overall system is controlled from a Sun workstation via the Ethernet. Each board includes 16 MB of dynamic memory (expandable to 64 MB) and 1 MB of fast static RAM. Theoretical peak performance is 128 MFLOPS/board, and test runs with the first working board show a sustained throughput of roughly one-third to one-half of this for algorithms of interest. Software development is aided by a Sun workstation-based command interpreter, tools from the standard C environment and a library of matrix and vector routines. >

The RAP: a ring array processor for layered network calculations

SPERT (synthetic perceptron testbed) is a fully programmable single chip microprocessor designed for efficient execution of artificial neural network algorithms. The first implementation is in a 1.2 mu m CMOS technology with a 50 MHz clock rate, and a prototype system is being designed to occupy a double SBus slot within a Sun Sparcstation. SPERT sustains over 300*10/sup 6/ connections per second during pattern classification, and around 100*10/sup 6/ connection updates per second while running the popular error backpropagation training algorithm. This represents a speedup of around two orders of magnitude over a Sparcstation-2 for algorithms of interest. An earlier system produced by the group, the Ring Array Processor (RAP), used commercial DSP chips. Compared with a RAP multiprocessor of similar performance, SPERT represents over an order of magnitude reduction in cost for problems where fixed-point arithmetic is satisfactory. >

SPERT: a VLIW/SIMD microprocessor for artificial neural network computations

A Single-Chip Fixed-Point Vector Microprocessor Is Described. The Chip Contains A Mips-Ii Risc Core With A 1 Kb Instruction Cache, Dual Eight-Way Parallel Vector Arithmetic Pipelines, A 128-Bit Memory Interface, And An 8-Bit Serial Host Interface. Each Vector Arithmetic Pipeline Contains A Cascade Of Six Functional Units That Can Be Dynamically Reconfigured By Each Instruction. The Resulting Peak Performance Is 4.3 Billion 32-Bit Arithmetic Operations Per Second At A Clock Speed Of 45 MHz.

http://ieeexplore.ieee.org/iel5/5468575/5468576/05468662.pdf

T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines

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