Jaesoo Ahn
Applied Materials
41 Papers
323 Citations
Jaesoo Ahn is an academic researcher from Applied Materials. The author has contributed to research in topics: Tunnel magnetoresistance & Layer (electronics). The author has an hindex of 16, co-authored 41 publications. Previous affiliations of Jaesoo Ahn include Stanford University & Samsung.
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Papers
New method for determining flat-band voltage in high mobility semiconductors
TL;DR: In this article, the flat-band voltage and capacitance of metal oxide semiconductor (MOS) capacitors are determined based on the point of inflection in the capacitance-voltage curve.
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A Study on Practically Unlimited Endurance of STT-MRAM
TL;DR: In this paper, the authors present a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases.
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Interface-State Modeling of $\hbox{Al}_{2}\hbox{O}_{3}$ –InGaAs MOS From Depletion to Inversion
Hanping Chen,Yu Yuan,Bo Yu,Jaesoo Ahn,Paul C. McIntyre,Peter M. Asbeck,Mark J. W. Rodwell,Yuan Taur +7 more
TL;DR: In this paper, a detailed analysis of the multifrequency capacitance and conductance-voltage data of MOS capacitors was presented, where the widely varied frequency dependence of the data from depletion to inversion can be fitted to various regional equivalent circuits derived from the full interface state model.
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Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance
Jimmy Kan,Chando Park,C. Ching,Jaesoo Ahn,Lin Xue,Wang Rongjun,A. Kontos,Liang Shurong,Mangesh Bangar,H. Chen,S. Hassan,S. Kim,Mahendra Pakala,Seung H. Kang +13 more
- 01 Dec 2016
TL;DR: In this paper, the authors present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays.
65
Patent
Hybrid carbon hardmask for lateral hardmask recess reduction
Kwon Thomas Jongwan,Cheng Rui,Abhijit Basu Mallick,Er-Xuan Ping,Jaesoo Ahn +4 more
- 04 Jan 2017
TL;DR: In this article, a plurality of hardmasks may be used in combination with patterning and etching processes to enable advanced device architectures, where a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon.
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