a b s t r a c t A bidimensional array based on single­photon avalanche diodes for triggered imaging systems is pre­ sented. The diodes are operated in the gated mode of acquisition to reduce the probability to detect noise counts interfering with photon arrival events. In addition, low reverse bias overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a stan­ dard HV­CMOS process gets rid of afterpulses and offers a reduced dark count probability by applying the proposed modes of operation. The detector exhibits a dynamic range of 15 bits with short gated ‘on’ periods of 10 ns and a reverse bias overvoltage of 1.0 V.

/pdf/a-gated-single-photon-avalanche-diode-array-fabricated-in-a-35cb8onsh2.pdf

A gated single­photon avalanche diode array fabricated in a conventional CMOS process for triggered systems

Large scale detectors in particle physics take many years to plan and to build. The last generation of large particle physics detectors for the energy frontier, ATLAS and CMS, have been operating for more than 10 years, and upgrades for them are now being done. Studies for the next generation of experimental facilities have been ongoing for a number of years. In this section future directions in integrated detector design are discussed, as they were visible at the time of writing this report.

/pdf/future-developments-of-detectors-4jllr49dpt.pdf

Future Developments of Detectors

High energy physics experiments require detectors with an excellent imaging performance. The innermost part is often a pixel vertex detector with 2D position readout. The DEPFET pixel detector is an option for the International Linear Collider and will be used in the Belle II experiment at the SuperKEKB accelerator in Japan. Two barrel layers
will be installed in a very conﬁned space and hence, a dense packaging of sensors, read-out and steering chips is mandatory. A hard radiation environment is inﬂuencing the electronics at the location close to the interaction point.

The steering chips are controlling the DEPFET imaging devices. They need to provide fast signals to read-out the large sensitive areas in a high speed. Two generations of steering chips are characterized and tested for their radiation hardness in this work. A converter chip was designed to operate the read-out chip stand-alone, until the data compression chip is ready.

The DEPFET detector modules will be build in the novel all-silicon approach, where the read-out and steering chips are mounted upside down directly onto the detector silicon. The silicon area is also used to interconnect the chips with the imaging devices and the cables. A thinned sensor area reduces the negative inﬂuences of the material on the particle tracks, but results in fragile devices.

A ﬂip-chip interconnection technology connects the chips to the detector and builds the all-silicon module. The technology has to be compatible with the thin and fragile DEPFET devices. Diﬀerent ﬂip-chip methods are evaluated in this dissertation. Many
processes are only feasible for mass production and can’t adopt to the ﬂexibility requirements in research and development. Two processes, the gold-stud and solder ball bumping, meet the requirements and were deployed in the scope of this work. Several test prototypes have been successfully built with these processes.

Interconnecting the ﬂip-chip mounted chips with the DEPFET array and the oﬀ-module cable connection on the detector modules is a further task addressed in this work. The special DEPFET technology limits the design complexity of the chip interconnection. A
high power consumption of the read-out chips and the dense packaging of chips on the module are increasing the complexity furthermore.

In summary, this work has provided an important contribution to the development of the novel high resolution DEPFET vertex detector concept and has advanced the construction of the Belle II pixel vertex detector.

Steering electronics, module design and construction of an all silicon DEPFET module

Monolithic pixel detectors integrating sensor matrix and readout in one piece of silicon have revolutionized imaging for consumer applications, but despite years of research they have not yet been widely adopted for high energy physics. Two major requirements for this application, radiation tolerance and low power consumption, require charge collection by drift for the most extreme radiation levels and an optimization of the collected signal charge over input capacitance ratio ( Q / C ). It is shown that monolithic detectors can achieve Q / C for low analog power consumption and even carryout the promise to practically eliminate analog power consumption, but combining sufficient Q / C , collection by drift, and integration of readout circuitry within the pixel remains a challenge. An overview is given of different approaches to address this challenge, with possible advantages and disadvantages.

Monolithic pixel detectors for high energy physics

Design and performance of improved column parallel CCD, CPC2

The Linear Collider Flavour Identification (LCFI) Collaboration is developing the sensors, readout electronics and mechanical support structures for the vertex detector of the International Linear Collider (ILC). High speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below the 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs), Column Parallel Readout chips (CPRs) and Column Parallel Driver chips (CPDs) have been developed. The CPCCD has to operate at a clock frequency of 50 MHz, which represents a difficult technical challenge due to the large sensor capacitance. The design and performance of the second generation CPCCD sensors, CPC2, and the new driver chip, CPD1, which meet these challenging requirements, are described.

Design and performance of improved Column Parallel CCD, CPC2

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Design and performance of improved column parallel CCD, CPC2

Design and performance of improved Column Parallel CCD, CPC2