J. Wolf
Fraunhofer Society
33 Papers
308 Citations
J. Wolf is an academic researcher from Fraunhofer Society. The author has contributed to research in topics: Layer (electronics) & Wafer. The author has an hindex of 12, co-authored 31 publications.
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Papers
TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules
Kai Zoschke,J. Wolf,Christina Lopper,I. Kuna,N. Jurgensen,V. Glaw,K. Samulewicz,J. Roder,Martin Wilke,O. Wunsch,M. Klein,M. v. Suchodoletz,Hermann Oppermann,Tanja Braun,Robert Wieland,Oswin Ehrmann +15 more
- 20 Jun 2011
TL;DR: In this article, the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer-level assembly with IC components are presented, and special focus is drawn on the TSV formation process including via etching, isolation and filling, front side high density wiring and subsequent backside processing of the thin TSV wafers.
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Thin film integration of passives - single components, filters, integrated passive devices
Kai Zoschke,J. Wolf,Michael Topper,Oswin Ehrmann,T. Fritzsch,K. Scherpinski,Herbert Reichl,F.-J. Schmuckle +7 more
- 01 Jun 2004
TL;DR: In this article, the authors investigated the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB).
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High power multichip modules employing the planar embedding technique and microchannel water heat sinks
Robert Hahn,A. Kamp,A. Ginolas,M. Schmidt,J. Wolf,V. Glaw,Michael Topper,Oswin Ehrmann,Herbert Reichl +8 more
- 28 Jan 1997
TL;DR: In this paper, the authors describe a novel packaging technology for high power multi-chip modules (MCMs) which provides access to the die backside for heat removal, the development of high performance microchannel heat sinks with a CTE matched to the MCM-substrate as well as a low thermal resistivity assembling technology of the two components.
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CrCu based UBM (under bump metallization) study with electroplated Pb/63Sn solder bumps - interfacial reaction and bump shear strength
TL;DR: In this article, the intermediate CrCu layer is modified using various sputtering techniques, and the underlying Cr adhesion layer is compared with TiW. The results demonstrate that the final Cu layer should have a minimum thickness, more than 0.8 /spl mu/m, for interface stability on CrCu based UBMs.
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Embedding technology-a chip-first approach using BCB
Michael Topper,K. Buschick,J. Wolf,V. Glaw,Robert Hahn,A. Dabek,Oswin Ehrmann,Herbert Reichl +7 more
- 09 Mar 1997
TL;DR: In this article, a planar embedding of bare dice and standard passive components was used to achieve a common, planar surface for PCB-based embedded circuits, where all components can be directly interconnected to the copper routing of the module.
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