The major obstacle which has limited the use of Vector Quantization (VQ) for real-time speech coding is the computationally demanding codebook-search algorithm. The essential task of this algorithm, pattern matching, has several properties which make it amenable to VLSI realization using a highly concurrent processor architecture. A VLSI pattern-matching chip provides the essential building-block for a specialpurpose codebook-search processor (CSP). The CSP can serve as a generic architecture for a variety of VQ-based speech coding applications. This paper reports on a working VQ processor for speech coding based on a first generation VLSI chip that efficiently performs the essential pattern-matching operation needed for the codebook-search process. Furthermore, the CSP architecture, using this chip, has been successfully incorporated into a compact single-board Vector PCM implementation which operates at rates between 7 and 18 kbits/s. A real-time Adaptive Vector Predictive Coder system using the CSP and augmented by a TMS-32010 programmable signal processor has been designed and recently implemented. We describe the structure of these two VQ coders and present experimental results obtained using the single-board Vector PCM coder.

Application of a VLSI Vector Quantization Processor to Real-Time Speech Coding

THE field of digital speech is rapidly coming to fruition as an area of opportunity for commercial application. In this paper we attempt to give a broad tutorial overview of some of the key aspects of this technology. We briefly outline some of the basic properties of speech and the techniques of coding that use these properties and point to areas of current research and areas of practical hardware implementation. We also attempt to outline some of the potential application areas for this new technology.

Current perspectives in digital speech

This survey of speech processing activities covers a period that began around 1971. Areas of importance - technical as well as historical - include speech recognition and understanding, speech coding, speaker recognition, and speech modification. A number of today's best-regarded techniques in speech and language processing stem from BBN's early work.

Speech processing at BBN

This paper introduces problems regarding design and implementation of a real-time floating point LPC vocoder running on a general purpose array processor. The implementation is intended to obtain a 2.4 kbit/s vocoder; the software structure however is designed in order to give the opportunity to change interactively the algorithms' parameters; moreover, it is also possible to change the vocoder microprogram structure including or excluding some functional blocks. A real-time measuring block is inserted as integral part of coder's microprogram; it checks continuously a given quantity, by updating a complete set of its statistical measurements, so constituting a unique tool both in testing and in system characterization phase. Architecture of the software and testing methodologies, are, then, the main novelties of the realization; moreover, the obtained features of the system, execution time and structure flexibility, make the implementation interesting and suggest more general issues too.

Design and test of a real-time floating point LPC vocoder

A single-board 16 kb/s and 32 kb/s APC speech coding terminal is described. The board is configurable as either two receivers, two transmitters, or a single-channel full-duplex coder. The terminal consists of two identical, independent TI TMS32020- based modules. Included in each module is a TMS32020, an analog I/O section, A/D/A conversion, digital I/O circuitry, static RAMs, and EPROMs. The board size is 5.6" × 6.0", and can be packaged in a standard secretarial desk phone shell. A software architecture using this hardware to implement the 16/32 kb/s Adaptive Predictive Coding with Hybrid Quantization (APCHQ) algorithm is described.

A single board multirate APC speech coding terminal

The feasibility of a speech coding algorithm is most effectively indicated by its successful real-time implementation. The implementation effort presents issues distinct from those related to the development of the algorithm. Problems of real-time software design and debugging, system reliability, and implementation correctness must be addressed. In addition, the power of a general purpose array processing computer may be required to accomplish the real-time aspect of the implementation. The unique, often highly parallel, architecture of available array processors can present the additional issues of multiprocessor intercommunication and control. This paper considers successful approaches to these issues in the context of two real-time speech coder algorithms implemented on an array processor, a linear predictive baseband coder operating at 9.6 kbits/s, and an adaptive predictive coder operating at 16 kbits/s.

Real-Time Speech Coder Implementation on an Array Processor

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Real-Time Speech Coder Implementation on an Array Processor