We present a bilayer cantilever microelectromechanical systems probe card configuration aiming to achieve an optimization of the mechanical and electrical properties of the probes. This bilayer cantilever structure is analyzed by an analytical method, and then further validated by finite element analysis. A prototype probe card structure is designed for the parallel I/O pads layout with a pitch of 100 µm, and developed via combining Si micromachining and ultraviolet Lithographie, Galvanoformung, Abformung (lithography, electroplating, and molding) (UV-LIGA) technique. The measured spring constant of the cantilever is 0.6362 Nm-1, close to the theoretical prediction. The resistance from the probe tip to the end of the Cu conductive line is as low as 0.035 , indicating a very small electrical loss on the probe structure. In the radio frequency (rf) range of 0 to 40 MHz, the characteristic impedance is higher than 20 k, while the capacitance between two adjacent probes is around 0.13 pF. These measurement data indicate that the designed cantilever probe card structure has a good rf isolation property that makes it suitable for the testing of high-speed signal ICs.

Design and fabrication of a micromachined bilayer cantilever probe card

The uniformity and deformation of electrochemical deposition (ECD) bumps get more and more important with the pitch shrinking and density increasing according to the requirement of modern electronic industry. In this paper, wafer level diameter and thickness distribution, surface roughness and hardness of Au bumps were characterized under different electroplating current densities and bath temperatures. Some valuable results were obtained. First, the diameter of ECD Au bumps was enlarged for 5–30 μm at all positions on the wafer for both the bumps of 10–100 μm diameters. Electroplated at 40 °C, the diameter distribution of Au bumps was similar to that of photoresist. While electroplated at 60 °C, its distribution was more symmetric. Second, more uniform thickness distribution of Au bumps was obtained when the bath temperature increased from 40 to 60 °C or the electroplating current density decreased from 8 to 3 mA/cm2. Third, the Au bumps electroplated at 60 °C exhibited the surface roughness of 105–125 nm independent of electroplating current densities. The Au bumps electroplated at 40 °C exhibited the surface roughness of 40–45 nm for 3 mA/cm2 and 5 mA/cm2 and 923.45 nm for 8 mA/cm2. Fourth, the hardness of Au bumps decreased with electroplating temperature increasing from 40 to 60 °C. The difference of hardness got at between 40 and 60 °C can be vanished by the following anneal process at 60 °C. In addition, the big differences among different current densities electroplated at 40 °C can also be vanished by the anneal process. Finally, possible reasons leading to above results were discussed.

Profile of the wafer level ECD gold bumps under variable parameters

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Profile of the wafer level ECD gold bumps under variable parameters