J. Snare
IBM
6 Papers
66 Citations
J. Snare is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Gate oxide. The author has an hindex of 5, co-authored 6 publications.
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Papers
A high-performance 0.08 /spl mu/m CMOS
L. Su,S. Subbanna,Emmanuel F. Crabbe,Paul D. Agnello,E. Nowak,R. Schulz,Stewart E. Rauch,Hung Y. Ng,T. Newman,A. Ray,M. Hargrove,A. Acovic,J. Snare,S. Crowder,Bomy A. Chen,J.Y.-C. Sun,Bijan Davari +16 more
- 11 Jun 1996
TL;DR: In this paper, the authors demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (Vsub dd < 1.5 V) with the best current drive at a given off-current reported in the literature to date.
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A high-density 6.9 sq. /spl mu/m embedded SRAM cell in a high-performance 0.25 /spl mu/m-generation CMOS logic technology
S. Subbanna,Paul D. Agnello,Emmanuel F. Crabbe,R. Schulz,S. Wu,Kurt A. Tallman,M.J. Saccamango,Stephen E. Greco,Vincent J. McGahay,A.J. Allen,B. Chen,T. Cotler,E. Eld,J. Lasky,H. Ng,Asit Kumar Ray,J. Snare,L. Su,D. Sunderland,Jonathan Z. Sun,Bijan Davari +20 more
- 08 Dec 1996
TL;DR: To this knowledge, this is the smallest reported SRAM cell in a salicide-only technology, and is achieved using deep-UV lithography, shallow-trench isolation, damascene tungsten low-resistance local interconnect, and optimization of design-rules.
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Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology
S.K.H. Fung,Mukesh Khare,Dominic J. Schepis,Woo-Hyeong Lee,S.H. Ku,H. Park,J. Snare,Bruce B. Doris,Atul C. Ajmera,Karl Paul Muller,Paul D. Agnello,Percy V. Gilbert,Jeffrey J. Welser +12 more
- 02 Dec 2001
TL;DR: In this paper, a super-HALO design on 45 nm SOI substrate is presented for the 100 nm technology node, which gives a drive current of 1000 (1100) /spl mu/A/A//spl µ/m DC (dynamic) for NFET and 445 (457)/spl m/a/m dc for PFET at an off current of 300 nA/m. The intrinsic gate delays are 0.55 ps and 1.19 ps.
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High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering
H. Park,Werner A. Rausch,Henry K. Utomo,K. Matsumoto,H. Nii,Shigeru Kawanaka,Philip A. Fisher,Sang Hyun Oh,J. Snare,William F. Clark,Anda Mocuta,Judson R. Holt,R. Mo,T. Sato,Dan Mocuta,Byoung Hun Lee,Omer H. Dokumaci,P. O'Neil,D. Brown,J. Suenaga,Li Yulong,L. Brown,J. Nakos,K. Hathorn,Paul Ronsheim,H. Kimura,Bruce B. Doris,G. Sudo,K. Scheer,Steven W. Mittl,Tina Wagner,T. Umebayashi,M. Tsukamoto,Y. Kohyama,J. Cheek,I. Yang,H. Kuroda,Yoshiaki Toyoshima,John Pellerin,Dominic J. Schepis,Paul D. Agnello,Jeffrey J. Welser +41 more
- 01 Jan 2003
TL;DR: In this article, the authors presented enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL process.
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Gate postdoping to decouple implant/anneal for gate, source/drain, and extension: maximizing polysilicon gate activation for 0.1 /spl mu/m CMOS technologies
Heemyong Park,Dominic J. Schepis,Anda Mocuta,Mukesh Khare,Li Yulong,Bruce B. Doris,S. Shukla,T. Hughes,Omer H. Dokumaci,Shreesh Narasimha,S.K.H. Fung,J. Snare,Byoung Hun Lee,James Chingwei Li,Paul Ronsheim,Anthony G. Domenicucci,Patrick R. Varekamp,Atul C. Ajmera,Jeffrey W. Sleight,P. O'Neil,Edward P. Maciejewski,Christian Lavoie +21 more
- 11 Jun 2002
TL;DR: In this paper, a gate postdoping method was proposed to decouple implant and anneal for gate, source/drain, and extension, which successfully reduced the poly depletion effect and thus the equivalent gate oxide thickness in inversion by up to /spl sim/2 /spl Aring/33% over a conventional process.
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