Existing models of electrical contacts are often inapplicable at the nanoscale because there are significant differences between nanostructures and bulk materials arising from unique geometries and electrostatics. In this Review, we discuss the physics and materials science of electrical contacts to carbon nanotubes, semiconductor nanowires and graphene, and outline the main research and development challenges in the field. We also include a case study of gold contacts to germanium nanowires to illustrate these concepts.

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Electrical contacts to one- and two-dimensional nanomaterials

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

An extremely low contact resistivity of 6-7 × 10-9 Ω·cm2 between Ni0.9Pt0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation. In this scheme, the implantation of B or As is performed into silicide followed by a low-temperature drive-in anneal. Reduction of effective Schottky barrier height is manifested in the elimination of nonlinearities in IV characteristics.

Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

In this work we present a potential solution for forming ultra-shallow junctions with extremely low contact resistivities in which dopants are implanted into silicides and diffused to the semiconductor interface using low temperature anneals. Conventional silicide process requires a fine tuning of silicide thickness and deep source/drain doping profile to achieve low contact resistance and low source/drain diffusion sheet resistance. With the silicide implantation approach, we show that they can be engineered independently, providing a larger design space for the reduction of total external resistance. We demonstrate that contact resistance for NiPt silicide can be significantly reduced down to 7×10−9 Ω-cm2 for p+ Si and 6×10−9 Ω-cm2 for n+ Si by using Schottky Barrier Height (SBH) tuning through the implantation of B/As into pre-formed NiPtSi followed by low-temperature drive-in annealing (see Fig. 1 for the process flow). Moreover, we find that the same low contact resistance can be achieved for both heavily and moderately doped junctions, which grants an additional degree of freedom in junction design to reduce series resistance. With this technology, the ultra-shallow junction process can be simplified to the formation of ultra-thin silicide followed by shallow implantation and low temperature RTA (<600C) without any demand of ultra-high thermal budget for the S/D doping. Implantation into silicides, as an alternative to surface implantation prior to silicidation, prevents silicide morphology degradation (encroachment, roughness, or inverted pyramids) induced by extra defects from the surface implantation.

Effective Schottky Barrier lowering for contact resistivity reduction using silicides as diffusion sources

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Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

Effective Schottky Barrier lowering for contact resistivity reduction using silicides as diffusion sources