It has been reported that high-temperature (/spl sim/1100/spl deg/C) N/sub 2/O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900/spl sim/950/spl deg/C) N/sub 2/O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO/sub 2/ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60/spl sim/110 /spl Aring/ gate oxides, a certain amount of nitrogen (/spl sim/2.2%) incorporated near the Si/SiO/sub 2/ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate. >

Suppression of boron penetration in p/sup +/ polysilicon gate P-MOSFETs using low-temperature gate-oxide N/sub 2/O anneal

Different oxynitride gate dielectrics (NH/sub 3/-nitrided, reoxidized NH/sub 3/-nitrided, N/sub 2/-annealed NH/sub 3/-nitrided, and N/sub 2/O grown oxides) are investigated for use in p/sup +/-polysilicon gate MOS devices. The comparison is based on flatband voltage shift as well as decrease in inversion capacitance. Results show that NH/sub 3/-nitrided and N/sub 2/-annealed NH/sub 3/-nitrided oxides best suppress the boron penetration and, consequently, these two undesirable effects. These findings are explained on the basis of the distribution of nitrogen in various oxynitride dielectrics. >

Oxynitride gate dielectrics for p/sup +/-polysilicon gate MOS devices

A brief review of the main physical phenomena involved in the cryogenic operation of CMOS silicon devices down to liquid helium temperature is given. Going from solid state physics towards electrical engineering point of views, several aspects such as the quantification of the inversion layer, the electronic transport in the 2D electron or hole gases, the scattering mechanisms, the impurity freeze-out in the substrate or in the lightly doped source and drain regions, the field-assisted impurity and impact ionization phenomena, the influence of series resistance and other parasitic effects (kink effect, hysteresis, transient, …) which alter the device characteristics will be discussed. The short channel effects such as drain induced barrier lowering, punch through, velocity overshoot will also be addressed.

Brief review of the MOS device physics for low temperature electronics

We report on a quantitative study of boron penetration from p/sup +/ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O/sub 2/ or N/sub 2/O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N/sub B/, for thicknesses other than those measured. We find that the minimum t/sub ox/ required to inhibit boron penetration is always 2-4 nm less when N/sub 2/O-grown gate oxides are used in place of O/sub 2/- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t/sub ox/, incremental variations in oxide thickness result in a large variation in N/sub B/, leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10/sup 11/ cm/sup -2/.

Thickness dependence of boron penetration through O/sub 2/- and N/sub 2/O-grown gate oxides and its impact on threshold voltage variation

MOSFET's with ultrathin (5 to 8.5 nm) silicon oxynitride gate film prepared by low-pressure rapid thermal chemical vapor deposition (RTCVD) using SiH/sub 4/, N/sub 2/O and NH/sub 3/ gases, are studied by low-frequency noise measurements (1 Hz up to 5 kHz). The analysis takes into account the correlated mobility fluctuations induced by those of the interfacial oxide charge. The nitrogen concentration, determined from SIMS analysis, varies from 0 to 11% atomic percentage. A comparison of the electrical properties between thermal and silicon oxynitride films is presented. The increasing LF noise signal with nitrogen atomic percentage indicates the presence of a higher density of slow interface traps with increasing nitrogen incorporation. Besides, a higher Coulomb scattering rate due to the nitridation induced interface charge explains reasonably well the degradation of the low field mobility after nitridation.

Low-frequency noise characterization of n- and p-MOSFET's with ultrathin oxynitride gate films

The ability of thin reoxidized nitrided oxide (ONO) gate dielectrics formed by rapid thermal processing to act as a barrier to boron penetration resulting from p/sup +/ poly gate processing are investigated. Measurements comparing the threshold voltage instability of capacitors fabricated with BF/sub 2/ implanted poly gates subjected to various postgate thermal cycles have been performed. The ONO gate dielectrics are found to be an excellent impurity barrier to boron diffusion, even in the presence of fluorine. The extent of the nitridation is also found to affect the diffusion barrier properties, with the highest temperature nitridations forming the best barriers. Reoxidation of the nitrided films reduces the barrier properties somewhat, but improvement is still observed over SiO/sub 2/. >

Impurity barrier properties of reoxidized nitrided oxide films for use with P/sup +/-doped polysilicon gates

The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K. >

Optimization of LDD devices for cryogenic operation

Previously, in detailed characterization of the NMOS cryogenic hot-carrier failure mode, major deviations from room temperature behavior were found However, to date, no similar detailed analysis of the PMOS cryogenic hot-carrier effect has been performed The purpose of this work is to investigate the PMOS hot carrier effect at cryogenic temperatures One of our primary findings shows that PMOS devices aged at low temperatures can undergo a drastic rebound-like effect that results in distinct reduction in device drive and large threshold voltage shift PMOS degradation of this degree is not observed for room temperature hot-carrier aging Charge pumping measurements are used to measure the different behaviors with 77 K and 300 K hot-carrier stressing Although the initial damage appears similar (same gm increase and Vt shift with stress time), subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K Low temperature stressing initially induces the typical room temperature gm increase due to channel length shortening caused by trapped electrons However, low-temperature stressing also appears to induce hole generation and substantial interface state creation unlike 300 K stressed devices This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures >

PMOS hot-carrier rebound and degradation

Experimental It is well established that the worst case bias condition for n-MOSFET hot carrier induced device degradation at room temperature is that corresponding to maximum substrate current (vg"l/2vd) However, we find that the worst caSe bias condition changes to maximum gate bias (i e Vg'vd) at low temperature In addition, the activation energy of hot carrier lifetime changes with implying the dominant hot carrier damage mechanism is a function of temperature Among other findings, we also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature

http://ieeexplore.ieee.org/iel2/1032/7499/00307457.pdf

Bias and Temperature Dependence of Hot Carrier Lifetime from 77K to 300K

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Papers

Impurity barrier properties of reoxidized nitrided oxide films for use with P/sup +/-doped polysilicon gates

Optimization of LDD devices for cryogenic operation

PMOS hot-carrier rebound and degradation

Bias and Temperature Dependence of Hot Carrier Lifetime from 77K to 300K