J. Roder
Technical University of Berlin
5 Papers
54 Citations
J. Roder is an academic researcher from Technical University of Berlin. The author has contributed to research in topics: Wafer & Wafer-level packaging. The author has an hindex of 4, co-authored 5 publications.
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Papers
TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules
Kai Zoschke,J. Wolf,Christina Lopper,I. Kuna,N. Jurgensen,V. Glaw,K. Samulewicz,J. Roder,Martin Wilke,O. Wunsch,M. Klein,M. v. Suchodoletz,Hermann Oppermann,Tanja Braun,Robert Wieland,Oswin Ehrmann +15 more
- 20 Jun 2011
TL;DR: In this article, the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer-level assembly with IC components are presented, and special focus is drawn on the TSV formation process including via etching, isolation and filling, front side high density wiring and subsequent backside processing of the thin TSV wafers.
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Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration
Kai Zoschke,Matthias Wegner,Martin Wilke,N. Jurgensen,Christina Lopper,I. Kuna,V. Glaw,J. Roder,O. Wunsch,M. J. Wolf,Oswin Ehrmann,Herbert Reichl +11 more
- 01 Jun 2010
TL;DR: In this article, the authors describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing, which is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures.
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Experience in fabrication of multichip-modules for the ATLAS pixel detector
T. Fritzsch,R. Jordan,M. Töpper,J. Roder,I. Kuna,Mario Lutz,F. Defo Kamga,J. Wolf,O. Ehrmann,H. Oppermann,Herbert Reichl +10 more
TL;DR: In this article, the results of an optical inspection of more than 7600 readout chips are presented, and the reliability of the bump interconnections is even checked by thermal cycling and accelerated thermal aging.
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Technology Requirements for Chip-On-Chip Packaging Solutions
Michael Topper,Th. Fritzsch,V. Glaw,R. Jordan,Christina Lopper,J. Roder,Lothar Dietrich,Mario Lutz,H. Oppermann,Oswin Ehrmann,H. Reichl +10 more
- 20 Jun 2005
TL;DR: The focus of this paper will be the technology requirements for the realization of different kinds of chip-on-chip packages, including 3-D packaging using the existing WLP infrastructure.
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Coating techniques for 3D-packaging applications
Michael Topper,Martin Wilke,J. Roder,Thorsten Fischer,Ch. Lopper +4 more
- 30 Jul 2012
TL;DR: A comparison of different coating techniques has been compared in this paper: For spray-coating the polymer precursors have to be modified by dilution with appropriate solvents as discussed by the authors.
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