A single Photon Counting pixel detector readout Chip (PCC) has been derived from previous work in the CERN RD19 collaboration for particle physics tracking devices, recently developed for high energy physics experiments. The readout chip is a 64 x 64 matrix of identical 170 {micro}m x 170 {micro}m cells. It is to be bump-bonded to an equally segmented 1 cm{sup 2} matrix of semiconductor sensors, e.g. Si or GaAs. Each readout cell comprises a preamplifier, a discriminator and a 15-bit counter. The input noise is 170 e{sup {minus}} rms. At the lowest nominal threshold of 1,400 e{sup {minus}} (5.1 keV in Si) the cells exhibit a threshold distribution with a spread before adjustment of 350 e{sup {minus}} rms. Each cell has a 5-bit register which allows masking, test-enable and 3-bit individual threshold adjust. After adjustment the threshold spread is reduced to 80 e{sup {minus}} rms. Absolute calibration of the electrically measured equivalent charge can be done once the readout chip is bump-bonded to a detector.

A Readout Chip for a 64 x 64 Pixel Matrix with 15-bit Single Photon Counting*

A new pixel readout prototype has been developed at CERN for high-energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 μm CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad–1.7 Mrad depending on the type of radiation. 10 keV X-rays, 60 Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed.

Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

Results are presented on hyperon and antihyperon production in Pb–Pb, pPb and pBe collisions at 158 GeV/c per nucleon. Λ, Ξ and Ω yields have been measured at central rapidity and medium transverse momentum as functions of the centrality of the collision. Comparing the yields in Pb–Pb to those in pBe interactions, strangeness enhancement is observed. The enhancement increases with the centrality and with the strangeness content of the hyperons, reaching a factor of about 20 for the Ω in the central Pb–Pb collisions.

Enhancement of hyperon production at central rapidity in 158-A-GeV/c Pb-Pb collisions

The field of pixel detectors has grown strongly in recent years through progress in CMOS technology, which permits many hundreds of transistors to be implemented in an area of 50–200 μm2. Pulse processing electronics with noise of the order of 100 e− RMS permits to distinguish photons of a few kilo-electron-Volts from background noise. Techniques are under development, which should allow single chip systems (area ∼1 cm2) to be extended to larger areas. This paper gives an introduction into the concept of quantum imaging using direct conversion in segmented semiconductor arrays. An overview of projects from this domain using strip, pad and in particular hybrid pixel detectors will be presented. One of these projects, the Medipix project, is described in more detail. The effect of different correction methods like threshold adjustment and flat field correction is illustrated and new measurement results and images are presented.

/pdf/development-of-segmented-semiconductor-arrays-for-quantum-jtxvwjr0wn.pdf

Development of segmented semiconductor arrays for quantum imaging

Progress in CMOS technology and in fine pitch bump bonding has made
possible the development of high granularity single photon counting detectors for
X-ray imaging. This thesis studies the design a ...

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

A second version of the Omega pixel readout chip has been developed in order to make it compatible with large area coverage. Specific features of the new chip include a reset which can be applied immediately following a “false” trigger, an improved minimum strobe time of ∼ 100 ns, a readout clock rate of ∼ 20 MHz and tri-state buffers on the output data lines. The excellent performance figures of the first chip for noise (100 e rms without detector and 170 e rms with detector) and power consumption (30 μW/pixel) have been maintained. We demonstrate how with solder bump-bonding we can create hybrid “ladders” which hermetically cover an area of ∼ 5 mm × 50 mm. Potential problems of electrical matching and yield have been addressed and procedures are in place for selecting only “good” readout chips for mounting.

Development of a pixel readout chip compatible with large area coverage

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Development of a pixel readout chip compatible with large area coverage