Several approaches to the heteroepitaxial growth of InP on (100)Si employing an electrochemically etched Si mesa, SiO2 masks, and a maskless procedure were investigated with the objective of achieving area-selective InP integration into Si metal-oxide-semiconductor (Si-MOS) technology. Maskless InP/Si device layer growth by metal-organic vapour-phase epitaxy with good selectivity on a structured InP buffer layer, surrounded by oxide, was achieved. Undesired InP depositions were removed with an SiO2 emulsion, spun on prior to InP growth. To study the effects on the Si-based electronics, p-metal-oxide-semiconductor field-effect tansistors (MOSFETs) were exposed to the various stages of the heteroepitaxial InP growth process. We have studied the influence of hydride atmospheres and thermal anneals on their electrical performance. A standard InP-on-(100)Si growth procedure was found to be acceptable for the MOS components, as demonstrated by a Schmitt-trigger laser-diode driver circuit.

Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits

A receiving apparatus is provided, which includes: a photoelectric detector (PD), adapted to generate current signals according to optical signals projected on the PD and digitally modulated at a high or low rate; a first switch, adapted to switch to output the high-rate or low-rate current signals; a first transimpedance amplifier (TIA), adapted to amplify the high-rate current signals into high-rate voltage signals; and a second TIA, adapted to amplify the received low-rate current signals into low-rate voltage signals. Therefore, in the present invention, high-rate and low-rate receiving paths are completely separated. This provides signals with good quality and avoids signal deterioration; and switching between the high-rate and low-rate receiving paths simplifies the structure and lowers costs.

Receiving apparatus and receiving method

A comparison between MOCVD grown AlGaAs/GaAs and InGaP/GaAs HBTs showed a relatively constant DC current gain as a function of temperature upto 300/spl deg/C for the latter devices. A novel high temperature ohmic contact using ZrB/sub 2/ diffusion barrier has been developed and found to be suitable for HBTs operating at elevated temperatures. This barrier has been successfully employed in the fabrication of InGaP/GaAs HBTs which operated at 200/spl deg/C for 18 hours without any significant change to device performance.

Characteristics of AlGaAs/GaAs and InGaP/GaAs HBTs at high temperature

Long-wavelength optoelectronic integrated circuits (OEICs) will be important components for future telecommunications systems for example as low-cost optical receivers or as nodes on high-speed optical networks. This paper reports the application of selective-area epitaxy (SAE) to the fabrication of monolithic GaAs-on-InP, long-wavelength OEICs incorporating optical detectors and transmitters together with digital and analogue electronics. The authors believe that this approach has produced the highest functionality long-wavelength OEICs fabricated to date.

Selective-area epitaxy for GaAs-on-InP optoelectronic integrated circuits (OEICS)

This paper presents a comparative analysis of the parameters of non-alloyed Pd/Ge/Ta/Cu and alloyed Ge/Au/Ni/Ta/Au ohmic contacts to n+-GaAs, both with planar as well planar and sidewall diffusion barriers based on Ta films formed by magnetron sputtering. It has been found that use of sidewall diffusion barriers reduces the value of specific contact resistance of ohmic contacts of both types and improves the thermal stability of the edge morphology of the contact pad in the case of alloyed Ge/Au/Ni/Ta/Au ohmic contacts. The effects observed for the samples with effective diffusion barrier are explained by limiting diffusion, as well as limiting the interaction of Au or Cu atoms with underlying metallization layers and with gallium arsenide, taking place along the sidewall surfaces of the ohmic contact.

Ohmic contacts to n + -GaAs with refractory metal sidewall diffusion barrier

Barrier layers have been used on top of Ni-Au-Ge alloyed and Pd-Ge ``non-alloyed'' ohmic contacts for GaAs MESFET integrated circuits. They prevent diffusion of subsequent interconnection layers and so maintain stable low resistance (0.05 ohm. mm) contacts. The assessment of these contact structures, both electrically and using AES and TEM, is presented. The results show that the barrier action is effective in producing uniform and reliable contacts and good yields of MSI high speed digital circuits.

/pdf/diffusion-barrier-layers-for-ohmic-contacts-to-gaas-4iph7zv0i3.pdf

Diffusion Barrier Layers for Ohmic Contacts to GaAs

A monolithic GaAs-on-InP, four channel, variable bandwidth, photo-receiver has been fabricated. This is the first application of a seeded mask technology, to improve the characteristics of patterned growth of integrated optical and electronic devices. This approach, which is compatible with atmospheric pressure MOVPE growth, may also be applied to lattice matched electronics or other optical components,e. g. lasers and waveguides. High frequency data from these fully functional OEICs is reported.

Fabrication of a GaAs-on-InP, four channel variable bandwidth optical receiver, opto-electronic integrated circuit (OEIC), using a seeded-mask technology

The development of Optoelectronic Integrated Circuits (OEICs) using planar integration technologies for good yields of fine linewidth (1?m) FETs and novel notch PIN diodes is discussed. In particular the horizontal integration of a GaAs MESFET circuit with a PIN diode is demonstrated and used to produce single and four channel receivers. These circuits have good sensitivities (-29.3dBm at 250Mbit/s) and represent state of the art levels of integration.

Planar Integration Technologies for Optoelectronic Integrated Circuits

Optical annealing and zirconium diboride barrier layers have been optimised for Ni, Au, Ge alloyed ohmic contacts to n-GaAs. Contact resistances of below 0.06 ?mm with a standard deviation of 0.02 ?mm were attained across a 50 mm diameter wafer. MESFETs produced using this new technology have shown very good characteristics and minimal degradation after temperature stressing at 300°C for 100 h. Fully-functional yields of 32% were obtained for high speed MSI circuits with 15 mm gate width. The very stable and low contact resistance of these optically annealed zirconium diboride contacts combined with the high yield and good circuit performance demonstrate the suitability of these contacts for use in GaAs high-speed circuits.

Optical annealing of ohmic contacts for GaAs high-speed integrated circuits using a zirconium diboride barrier layer

The fabrication of a monolithic GaAs-on-InP, four channel, variable-bandwidth photoreceiver using seeded mask technology is discussed. The method, which is compatible with atmospheric metalorganic vapor-phase epitaxy (MOVPE) growth, may be applied to lattice matched electronics for other optical components. High-frequency data from fully functional OEICs are reported. >

Horizontal integration fabrication of a GaAs-on-InP opto-electronic integrated circuit (OEIC) using seeded-mask technology: four channel variable bandwidth optical receiver

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