VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by demanding signal processing and networking applications. However, in order to take advantage of the available processing and communication resources, an optimal mapping of the application tasks onto the platform resources is of crucial importance. In this paper, we propose a SystemC-based simulation framework, which enables the quantitative evaluation of application-to-platform mappings by means of an executable performance model. Key element of our approach is a configurable event-driven Virtual Processing Unit to capture the timing behavior of multi-processor/multi-threaded MP-SoC platforms. The framework features an XML-based declarative construction mechanism of the performance model to significantly accelerate the navigation in large design spaces. The capabilities of the proposed framework in terms of design space exploration is presented by a case study of a commercially available MP-SoC platform for networking applications. Focussing on the application to architecture mapping, our introduced framework highlights the potential for optimization of an efficient design space exploration environment.

/pdf/a-modular-simulation-framework-for-spatial-and-temporal-task-3d2g2tgut0.pdf

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms

The increasing demands of high-performance in embedded applications under shortening time-to-market has prompted system architects in recent time to opt for multi-processor systems-on-chip (MP-SoCs) employing several programmable devices. The programmable cores provide a high amount of flexibility and reusability, and can be optimized to the requirements of the application to deliver high-performance as well. Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative. In this paper, we propose a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle. Unlike traditional SoC design flows where software design starts only after the initial SoC architecture is ready, our framework allows a co-development of the hardware and the software components in a tightly coupled loop where the hardware can be refined by considering the requirements of the software in a stepwise manner. The key element of this framework is the integration of a fine-grained software instrumentation tool into a system-level-design (SLD) environment to obtain accurate software performance and memory access statistics. The accuracy of such statistics is comparable to that obtained through instruction set simulation (ISS), while the execution speed of the instrumented software is almost an order of magnitude faster than ISS. Such a combined design approach assists system architects to optimize both the hardware and the software through fast exploration cycles, and can result in far shorter design cycles and high productivity. We demonstrate the generality and the efficiency of our methodology with two case studies selected from two most prominent and computationally intensive embedded application domains.

/pdf/a-sw-performance-estimation-framework-for-early-system-level-6ksrkbgjrl.pdf

A SW performance estimation framework for early system-level-design using fine-grained instrumentation

Purpose




This paper provides a critical review of developments in the adaptability of buildings. The purpose of this paper is to determine the current “state-of-the-art”, describe current thinking and trends in research and practice, and identify issues and gaps that further research can address. It provides a basis for a scientific and practical understanding of the interdependencies across different design criterion. This paper increases the awareness of architects, engineers, clients and users on the importance of adaptability and its role in lowering impacts over the lifecycle of buildings as part of the infrastructure system.




Design/methodology/approach




This paper draws mainly from the literature as its source of evidence. These were identified from established databases and search engines (e.g. Scopus, ISI Web of Knowledge and Google Scholar) using keywords such as adaptability, adaptable, adaptation, and flexibility. Over 80 sources including books, journal papers, conference proceedings, research reports and doctoral theses covering the period 1990 to 2017 were reviewed and categorised. An inductive approach was used to critically review and categorise these publications and develop a framework for analysis.




Findings




The concept of adaptability includes many dimensions which can broadly fall into two categories: changes to buildings and user adaptations to buildings. However, previous research has mostly focussed on the former, with many attempts to identify building attributes that facilitate adaptability, and some considerations for its assessment. Key areas that have not been adequately addressed and which require further research include: user/occupant adaptations, cost, benefits and implications of various adaptability measures, and the development of a standardised assessment methodology that could aid in decision making in the design stage of buildings.




Research limitations/implications




The adaptability strategies considered in this review focussed mainly on building components and systems, and did not include the contribution of intelligent and smart/biological systems. The coverage is further limited in scope due to the period considered (1990-2017) and the exclusion of terms such as “retrofit” and “refurbishment” from the review. However, the findings provide a solid basis for further research in the areas identified above. It identifies research issues and gaps in knowledge between the defined needs and current state-of-the-art on adaptive building for both research and practice.




Originality/value




This paper is a review of research into a highly topical subject, given the acknowledged need to adapt buildings over their lifecycle to environmental, economic or social changes. It provides further insights on the dimensions of adaptability and identifies areas for further research that will contribute to the development of robust tools for the assessment of building adaptability, which will enhance the decision-making process of building design and the development of a more sustainable built environment.

/pdf/a-critical-review-of-the-developments-in-building-x7vf0cj4x1.pdf

A critical review of the developments in building adaptability

Single-chip heterogeneous multiprocessors (SCHMs) are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs traditionally targeted by the design automation community, general-purpose designs traditionally targeted by the computer architecture community, nor pure embedded designs traditionally targeted by the real-time community. An entirely new design philosophy will be needed for this hybrid class of computing. The programming of the device will be drawn from a narrower set of applications with execution that persists in the system over a longer period of time than for general-purpose programming. However, the devices will still be programmable, not only at the level of the individual processing element, but across multiple processing elements and even the entire chip. The design of other programmable single chip computers has enjoyed an era where the design tradeoffs could be captured in simulators such as SimpleScalar and performance could be evaluated to the SPEC benchmarks. Motivated by this, we describe new benchmark-based design strategies for SCHMs which we refer to as scenario-oriented design. We include an example and results

Scenario-oriented design for single-chip heterogeneous multiprocessors

Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Currently, the most accurate methods of simulating the interactions between these components operate at the cycle-accurate level, which can be very slow to execute for large systems. Analytical models sacrifice accuracy for speed, and cannot cope with dynamic data-dependent behavior well. We propose a hybrid approach combining simulation with piecewise evaluation of analytical models that apply time penalties to simulated regions. Our experimental results show that for representative heterogeneous multiprocessor applications, simulation time can be decreased by 100 times over cycle-accurate models, while the error can be reduced by 60% to 80% over traditional analytical models to within 18% of an ISS simulation.

http://www.ece.vt.edu/jmpaul/schm-pubs/DATE04.pdf

Modeling shared resource contention using a hybrid simulation/analytical approach

Single chip heterogeneous multiprocessors (SCHMs) are becoming more commonplace, especially in portable devices where reduced energy consumption is a priority. The use of coordinated collections of processors which are simpler or which execute at lower clock frequencies is widely recognized as a means of reducing power while maintaining latency and throughput. A primary limitation of using this approach to reduce power at the system level has been the time to develop and simulate models of many processors at the instruction set simulator level. High-level models, simulators, and design strategies for SCHMs are required to enable designers to think in terms of collections of cooperating, heterogeneous processors in order to reduce power. Toward this end, this paper has two contributions. The first is to extend a unique, preexisting high-level performance simulator, the Modeling Environment for Software and Hardware (MESH), to include power annotations. MESH can be thought of as a thread-level simulator instead of an instruction-level simulator. Thus, the problem is to understand how power might be calibrated and annotated with program fragments instead of at the instruction level. Program fragments are finer-grained than threads and coarser-grained than instructions. Our experimentation found that compilers produce instruction patterns that allow power to be annotated at this level using a single number over all compiler-generated fragments executing on a processor. Since energy is power*time, this makes system runtime (i.e., performance) the dominant factor to be dynamically calculated at this level of simulation. The second contribution arises from the observation that high-level modeling is most beneficial when it opens up new possibilities for organizing designs. Thus, we introduce a design strategy, enabled by the high-level performance power-simulation, which we refer to as spatial voltage scaling. The strategy both reduces overall system power consumption and improves performance in our example. The design space for this design strategy could not be explored without high-level SCHM power-performance simulation.

http://www.ece.vt.edu/jmpaul/schm-pubs/tc.pdf

Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors

Multiple-detect test sets detect single stuck line faults multiple times, and thus have a higher probability of detecting complex defects. But current definitions of what constitutes a new test for a single stuck line fault do not leverage defect locality. Recent work has proposed a new metric to capture quality of a multiple-detect test set based on the number of unique states on lines in the physical neighborhood of a targeted line. This paper presents a new ATPG strategy that uses this metric to generate higher quality multiple-detect test sets.

Multiple-detect ATPG based on physical neighborhoods

A variety of yield-learning techniques are essential since no single approach can effectively find every manufacturing perturbation that can lead to yield loss. Test structures, for example, can range from being simple in nature (combs and serpentine structures for measuring defect-density and size distributions) to more complex, active structures that include transistors, ring oscillators, and SRAMs. Test structures are designed to provide seamless access to a given failure type: its size, its location, and possibly other pertinent characteristics.

Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations

Power-Performance Simulation and Design Strategies for Single-Chip

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