A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N/sup +/, P/sup +/, Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-gate poly-Si/sub 1-x/Ge/sub x/-gated (x=0 or 0.25) CMOS devices for various gate oxide thicknesses. In addition, this model ran also be employed to determine the physical oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current).

Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling

We have performed an experiment proving that the widely accepted E-field TDDB model is a physically incorrect description of breakdown in ultrathin gate oxides. Although interface traps are the dominant SILC mechanism below 5 V stress, breakdown remains limited by bulk trap generation and is voltage-driven. It has been recently proposed that the anode hole injection model is still operative at low voltages. Although we will show that holes do generate bulk traps and cause breakdown in ultrathin oxides, hole injection does not completely account for all of the trap generation mechanisms observed during direct tunneling stress.

Experimental evidence for voltage driven breakdown models in ultrathin gate oxides

We investigate theoretically coherent electron tunneling through three-dimensional microscopic Si[100]/SiO2/Si[100] model junctions with oxide thicknesses between 0.4 and 4.6 nm. The transmission probabilities of these structures were calculated using a semiempirical tight-binding scattering method. Our calculations provide a basis for the microscopic understanding of the observed independence of tunneling transmission on the orientation of the bulk silicon and on the nature of inelastic defect-assisted tunneling. We document significant differences between transmission coefficients obtained with the present scheme and with the popular effective-mass-based approaches. The energy dependence of the effective tunneling mass in bulk silicon dioxide is predicted.

Tunneling through ultrathin SiO2 gate oxides from microscopic models

The density-gradient description of quantum transport is applied to the analysis of tunneling phenomena in ultrathin (<25 /spl Aring/) oxide MOS capacitors. Both electron and hole tunneling are included in the one-dimensional (1-D) analysis and two new refinements to density-gradient theory are introduced, one relating to the treatment of Shockley-Read-Hall recombination and the other a modification of the tunneling boundary conditions to account for the semiconductor bandgap. Detailed comparisons are made with experimental current-voltage (I-V) data for samples with both n/sup +/ and p/sup +/ polysilicon gates and all of the features of the data are found to be understandable within the density-gradient framework. Besides providing new understanding of these experiments, these results show that the density-gradient approach can be of great value for engineering-oriented device analysis in quantum regimes.

Density-gradient analysis of MOS tunneling

We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20% in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done.

/pdf/a-comparison-of-quantum-mechanical-capacitance-voltage-6tj86b0gof.pdf

A comparison of quantum-mechanical capacitance-voltage simulators

Physical gate oxide thickness is extracted from TiN gate PMOS and NMOS capacitance voltage measurements using an efficient multi-band Hartree self-consistent Poisson solver. The extracted oxide thicknesses are then used to perform direct tunneling current simulations. Excellent agreement between measured a simulated tunnel current is obtained without the use of adjustable fitting parameters.

Physical oxide thickness extraction and verification using quantum mechanical simulation

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Physical oxide thickness extraction and verification using quantum mechanical simulation