J. Conner
Freescale Semiconductor
4 Papers
72 Citations
J. Conner is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Silicon on insulator & Electron mobility. The author has an hindex of 3, co-authored 4 publications.
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Papers
Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors
A. V-Y Thean,Z-H Shi,Leo Mathew,Tab A. Stephens,H. Desjardin,Colita Parker,Ted R. White,Matthew W. Stoker,L. Prabhu,R. Garcia,B-Y. Nguyen,S. Murphy,Raj Rai,J. Conner,Bruce E. White,S. Venkatesan +15 more
- 01 Dec 2006
TL;DR: In this article, the performance and inter-die variability of doped and undoped channel multiple-gate FETs with respect to planar SOI devices were compared, and it was shown that doped-channel FinFETs have equivalent variability to narrow-width planar devices.
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Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance
H.-H. Tseng,Philip J. Tobin,E.A. Hebert,S. Kalpat,M. Ramon,L. R. C. Fonseca,Z.X. Jiang,James K. Schaeffer,Rama I. Hegde,Dina H. Triyoso,David C. Gilmer,W.J. Taylor,C. Capasso,Olubunmi O. Adetutu,D. Sing,J. Conner,E. Luckowski,B.W. Chan,A. Haggag,S. Backer,R. Noble,M. Jahanbani,Y.H. Chili,Bruce E. White +23 more
- 05 Dec 2005
TL;DR: Using a novel fluorinated TaxCy/high-k gate stack, this article showed breakthrough device reliability and performance improvements, which is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern.
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Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)
Aaron Thean,Da Zhang,Victor H. Vartanian,Vance H. Adams,J. Conner,M. Canonico,H. Desjardin,Paul A. Grudowski,B. Gu,Zhonghai Shi,S. Murphy,Gregory S. Spencer,S. Filipiak,Darren V. Goedeke,X.-D. Wang,Brian J. Goolsby,V. Dhandapani,L. Prabhu,S. Backer,L. B. La,D. Burnett,Ted R. White,Bich-Yen Nguyen,B. E. White,S. Venkatesan,J. Mogab,Ian Cayrefourcq,C. Mazure +27 more
- 02 Oct 2006
TL;DR: In this article, a biaxial-uniaxial hybridized strained CMOS (SC-SSOI) was proposed for sub-40nm devices with 30% reduction in gate leakage current, while introducing minimum process complexity.
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Uniaxial and Biaxial Strain for CMOS Performance Enhancement
Bich-Yen Nguyen,S. Zhang,Aaron Thean,Paul A. Grudowski,Victor H. Vartanian,Ted R. White,Stefan Zollner,David Theodore,Brian J. Goolsby,H. Desjardins,L. Prabhu,R. Garcia,John J. Hackenberg,V. Dhandapani,S. Murphy,R. Rai,J. Conner,P. Montgomery,Colita Parker,J. Hildreth,R. Noble,M. Jahanbani,D. Eades,Jon D. Cheek,B. E. White,J. Mogab,S. Venkatesan +26 more
- 15 May 2006
TL;DR: In this paper, the authors optimized the interaction between biaxial lattice strain and process-induced stressor and channel orientation for enhancing both short-channel SSOI NMOS and PMOS devices.
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