How can neural networks learn the rich internal representations required for difficult tasks such as recognizing objects or understanding language?

https://dl.acm.org/doi/pdf/10.1145/3448250

Deep learning for AI

SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine

A series of theoretical and experimental results have suggested that multilayer perceptrons (MLPs) are an effective family of algorithms for the smooth estimate of highly dimensioned probability density functions that are useful in continuous speech recognition. All of these systems have exclusively used context-independent phonetic models, in the sense that the probabilities or costs are estimated for simple speech units such as phonemes or words, rather than biphones or triphones. Numerous conventional systems based on hidden Markov models (HMMs) have been reported that use triphone or triphone like context-dependent models. In one case the outputs of many context-dependent MLPs (one per context class) were used to help choose the best sentence from the N best sentences as determined by a context-dependent HMM system. It is shown how, without any simplifying assumptions, one can estimate likelihoods for context-dependent phonetic models with nets that are not substantially larger than context-independent MLPs. >

/pdf/cdnn-a-context-dependent-neural-network-for-continuous-2zffdo8efa.pdf

CDNN: a context dependent neural network for continuous speech recognition

The Ring Array Processor: a multiprocessing peripheral for connectionist applications

The aim of this paper is to propose a new classification approach of artificial neural networks hardware. Our motivation behind this work is justified by the following two arguments: first, during the last two decades a lot of approaches have been proposed for classification of neural networks hardware. However, at present there is not a clear consensus on classification criteria and performances. Second, with the evolution of the microelectronic technology and the design tools and techniques, new artificial neural networks (ANNs) implementations have been proposed, but they are not taken into consideration in the existing classification approaches of ANN hardware. In this paper, we propose a new approach for classification of neural networks hardware. The paper is organized in three parts: in the first part we review most of existing approaches proposed in the literature during the period 1990---2010 and show the advantages and disadvantages of each one. In the second part, we propose a new classification approach that takes into account most of consensual elements in one hand and in the other hand it takes into consideration the evolution of the design technology of integrated circuits and the design techniques. In the third part, we review examples of neural hardware achievements from industrial, academic and research institutions. According to our classification approach, these achievements range from standard chips to VLSI ASICs, FPGA and embedded systems on chip. Finally, we enumerate design issues that are still posed. This could help to give new directions for future research work.

A new classification approach for neural networks hardware: from standards chips to embedded systems on chip

The authors have designed and implemented a ring array processor, RAP, for fast implementation of layered neural network algorithms. The RAP is a multi-DSP system targeted at continuous speech recognition using connectionist algorithms. Four boards, each with four Texas Instruments, TMS 320C30 DSPs, serve as an array processor for a 68020-based host running a real-time operating system. The overall system is controlled from a Sun workstation via the Ethernet. Each board includes 16 MB of dynamic memory (expandable to 64 MB) and 1 MB of fast static RAM. Theoretical peak performance is 128 MFLOPS/board, and test runs with the first working board show a sustained throughput of roughly one-third to one-half of this for algorithms of interest. Software development is aided by a Sun workstation-based command interpreter, tools from the standard C environment and a library of matrix and vector routines. >

The RAP: a ring array processor for layered network calculations

A ring array processor (RAP) designed for fast simulation of artificial neural network algorithms is described. The RAP is a multiprocessor system which is particularly targeted in the training of feedforward networks for the recognition of continuous speech. The overall system consists of several four-processor boards serving together as an array processor for a 68020-based host running a real-time operating system. The prototype design includes 64 Mbytes of dynamic memory (expandable to 256) and 4 Mbytes of fast static RAM distributed between 16 processors on four boards. Theoretical peak performance is 512 MFLOPS, and simulations have indicated a sustained throughput of roughly half of this for algorithms of current interest, including communication overhead of roughly 10-30%. Initial tests with the new hardware have confirmed the major assumptions of the estimates from the simulations. >

RAP: a ring array processor for multilayer perceptron applications

We are constructing a multiprocessor system for running connectionist simulations, particularly for layered networks. Programmable gate arrays are used to shift data along a communication ring with minimal processor intervention. The initial system is designed with 68 MBytes of memory distributed among an may of 16 floating pint DSP chips, with an aggregate peak performance of 512 MFlops. Expected communication overhead is no moTe than 10-209’0 for algorithms of current interest.

http://ieeexplore.ieee.org/iel5/8547/27032/01200742.pdf

A multi-DSP ring array for connectionist simulations

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The RAP: a ring array processor for layered network calculations

RAP: a ring array processor for multilayer perceptron applications

A multi-DSP ring array for connectionist simulations