Low dielectric constant polymers for microelectronics

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

A high performance interconnection network on a chip is essential to match the ever improving performance of the semiconductor devices they interconnect. This issue reviews the need, some fundamental background justifying the need, approaches one can take in trying to satisfy the need, and associated issues related to the concept of multilevel interconnection (MLI) technology for the ULSI/GSI era of the silicon integrated circuits, with emphasis on materials and the processes that will lead to an acceptable MLI scheme. Thus besides discussing the MLI concepts and implementation issues, properties of metals and their alloys (especially those of Cu and Al), diffusion barrier/adhesion promoter, interlayer dielectrics, deposition and etching of mateials, planarization issues, reliability issues, and new materials concepts are presented. Emphasis is obviously placed on the presently focused research on replacing aluminum with copper based interconnections. The author's viewpoint on gradual changes in replacing current materials with newer mateials as they become available is also presented. A synergism between the materials sets for on-chip and off-chip interconnections has been pointed out.

Multilevel interconnections for ULSI and GSI era

https://www.seas.ucla.edu/%7Epilon/Publications/Thin%20Solid%20Films2006.pdf

Effective optical properties of non-absorbing nanoporous thin films

Luft, Luft, Luft … und wenig festes Gerust, das ist die Grundlage fur eine interessante Materialklasse – die Aerogele (rechts schematisch gezeigt). Doch kann man deshalb von einer „leichten” Chemie reden? Das Design eines so filigranes Netzwerks bedarf einer auserst genauen Kontrolle und Einstellung der chemischen Parameter. Dank der Reichhaltigkeit der Variationsmoglichkeiten wird man dann aber mit einer Vielfalt von unterschiedlichen Eigenschaftsprofilen belohnt.

Aerogele – luftige Materialien: Chemie, Struktur und Eigenschaften

Low density silica xerogels have many properties which suggest their use as a low dielectric constant material. Recent process improvements to control capillary pressure and strength by employing aging and pore chemistry modification, such that shrinkage is minimal during ambient pressure drying, have eliminated the need for supercritical drying. Although xerogels offer advantages for intermetal dielectric (IMD) applications because of their low dielectric constant (<2), high temperature limit, and compatibility with existing microelectronics precursors and processes, they suffer from unanswered questions. These include: 1) are all pores smaller than microelectronics features, 2) what are their mechanical properties (for processing and particle generation), and 3) what is their thermal stability. We have produced bulk xerogels under similar conditions to those used for films and studied the effect of density on the pore size distribution and bulk modulus.

Preparation Of Low-Density Xerogels At Ambient Pressure For Low K Dielectrics

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Preparation Of Low-Density Xerogels At Ambient Pressure For Low K Dielectrics