Le secteur Semi-conducteurs avec l'avenement de fabrication submicroniques coule dessous de 45 nm ont commence a relever de nouveaux defis pour continuer a evoluer en fonction de la loi de Moore. En ce qui concerne l'adoption generalisee de systemes embarques une contrainte majeure est devenu la consommation d'energie de l'IC. En outre, les technologies de memoire comme le standard actuel de la technologie de memoire integre pour la hierarchie de la memoire, la memoire SRAM, ou le flash pour le stockage non-volatile ont des contraintes complexes extremes pour etre en mesure de produire des matrices de memoire aux nœuds technologiques 45 nm ci-dessous. Un important est jusqu'a present memoire non volatile n'a pas ete adopte dans la hierarchie memoire, en raison de sa densite et comme le flash sur la necessite d'un fonctionnement multi-tension.Ces theses ont fait, par le travail dans l'objectif de ces contraintes et de fournir quelques reponses. Dans la these sera presente methodes et les resultats extraits de ces methodes pour corroborer notre objectif de definir une feuille de route a adopter une nouvelle technologie de memoire non volatile, de faible puissance, a faible fuite, SEU / MEU-resistant, evolutive et avec similaire le rendement en courant de la SRAM, physiquement equivalente a SRAM, ou encore mieux, avec une densite de surface de 4 a 8 fois la surface d'une cellule SRAM, sans qu'il soit necessaire de domaine multi-tension comme FLASH. Cette memoire est la MRAM (memoire magnetique), selon l'ITRS avec un candidat pour remplacer SRAM dans un proche avenir. MRAM au lieu de stocker une charge, ils stockent l'orientation magnetique fournie par l'orientation de rotation-couple de l'alliage sans la couche dans la MTJ (Magnetic Tunnel Junction). Spin est un etat quantical de la matiere, que dans certains materiaux metalliques peuvent avoir une orientation ou son couple tension a appliquer un courant polarise dans le sens de l'orientation du champ souhaitee.Une fois que l'orientation du champ magnetique est reglee, en utilisant un amplificateur de lecture, et un flux de courant a travers la MTJ, l'element de cellule de memoire de MRAM, il est possible de mesurer l'orientation compte tenu de la variation de resistance, plus la resistance plus faible au passage de courant, le sens permettra d'identifier un zero logique, diminuer la resistance de la SA detecte une seule logique. Donc, l'information n'est pas une charge stockee, il s'agit plutot d'une orientation du champ magnetique, raison pour laquelle il n'est pas affecte par SEU ou MEU due a des particules de haute energie. En outre, il n'est pas du a des variations de tensions de modifier le contenu de la cellule de memoire, le piegeage charges dans une grille flottante.En ce qui concerne la MRAM, cette these a par adresse objective sur les aspects suivants: MRAM applique a la hierarchie de la memoire:- En decrivant l'etat actuel de la technique dans la conception et l'utilisation MRAM dans la hierarchie de memoire;- En donnant un apercu d'un mecanisme pour attenuer la latence d'ecriture dans MRAM au niveau du cache (Principe de banque de memoire composite);- En analysant les caracteristiques de puissance d'un systeme base sur la MRAM sur Cache L1 et L2, en utilisant un debit d'evaluation dedie- En proposant une methodologie pour deduire une consommation d'energie du systeme et des performances.- Et pour la derniere base dans les banques de memoire analysant une banque memoire Composite, une description simple sur la facon de generer une banque de memoire, avec quelques compromis au pouvoir, mais la latence equivalente a la SRAM, qui maintient des performances similaires.

https://tel.archives-ouvertes.fr/tel-01015187/document

Applications des technologies mémoires MRAM appliquées aux processeurs embarqués

Bi-directional write current for writing `1' and `0', and shared read and write current paths severely limit the design space of spin-transfer torque MRAMs (STT-MRAM). Failure mitigation techniques proposed in the literature may be insufficient for realizing the full potential of STT-MRAMs at scaled MTJ dimensions due to asymmetries in MTJ characteristics and in access transistor drive-ability. This paper shows how STT-MRAM based on multi-terminal structures can overcome some of the above design constraints, leading to robust low-power STT-MRAM suitable for on-chip cache applications.

Robust low-power multi-terminal STT-MRAM

Non-volatile magnetic storage, from 1940s magnetic core to present day racetrack memory and magnetic anisotropy switching devices rely on the metastability of magnetic domains to store information. However, the inherent inefficiency of converting the information-carrying charge current into magnetization switching sets fundamental limitations in energy consumption. Other non-magnetic non-volatile memories such as memristors, ferroelectric memory and phase change memory devices also rely on energetically relatively costly crystal structural rearrangements to store information. In contrast, conventional electronic charge states in quantum dots for example, can be switched in femtoseconds with high efficiency, but any stored information dissipates rapidly. Here we present a radically different approach in the form of a charge-configuration memory (CCM) device that relies on charge-injection-driven electronic crystal melting and topological protection of the resulting electronic domain configurations of a two-dimensional electronic crystal to store information. With multiprobe scanning tunneling microscopy (STM) we show microscopically, within an operational device, how dislocations in the domain ordering lead to metastability by a mechanism that is topologically equivalent to magnetic bubble memory. The devices have a very small switching energy (<2.2 fJ/bit), ultrafast switching speed of <11 ps and operational range over more than 3 orders of magnitude in temperature (<250 mK ~ 190 K). Together with their simple functionality, a large resistance switching ratio, straightforward fabrication and impressive endurance, CCM devices introduce a new memory paradigm in emerging cryo-computing and other high-performance computing applications that require ultrahigh speed and low energy consumption.

Energy efficient manipulation of topologically protected states in non-volatile ultrafast charge configuration memory devices

Current trends in data processing have given impetus for an intense search of new concepts of memory devices with emphasis on efficiency, speed, and scalability. A promising new approach to memory storage is based on resistance switching between charge-ordered domain states in the layered dichalcogenide 1T-TaS2. Here we investigate the energy efficiency scaling of such charge configuration memory (CCM) devices as a function of device size and data write time τW as well as other parameters that have bearing on efficient device operation. We find that switching energy efficiency scales approximately linearly with both quantities over multiple decades, departing from linearity only when τW approaches the ∼0.5 ps intrinsic switching limit. Compared to current state of the art memory devices, CCM devices are found to be much faster and significantly more energy efficient, demonstrated here with two-terminal switching using 2.2 fJ, 16 ps electrical pulses.

/pdf/charge-configuration-memory-devices-energy-efficiency-and-6891twbr.pdf

Charge Configuration Memory Devices: Energy Efficiency and Switching Speed

Since the initial prediction and experimental demonstration of magnetization reversal by spin transfer torque (STT), there has been continuous progress toward the development of nonvolatile magnetic random access memory based on STT switching (STT-RAM) in nanoscale magnetic tunnel junctions (MTJs). In the most common STT-RAM configuration shown in Fig. 1(a), the magnetic moments of the free layer and the pinned polarizing layer of an MTJ lie collinear to one another in the plane of the junction. In this configuration (in-plane STT-RAM or IST-RAM), STT is small during the initial stages of the free layer's magnetic moment reversal, resulting in a relatively long nanosecond-scale switching time. Switching can be greatly accelerated in an alternative STT-RAM configuration, in which a second polarizer with magnetic moment perpendicular to the MTJ plane is added to the magnetic multilayer (orthogonal STT-RAM or OST-RAM). The initial STT from the perpendicular polarizer is large and has been predicted to induce ultrafast precessional switching of the free layer's magnetization on a time scale of 100 ps. The differences in the reversal modes expected for the IST-RAM and OST-RAM devices are illustrated in Figs. 1(c) and 1(d), wherein magnetization switching trajectories are shown for the two types of memory.

Ultrafast spin torque memory based on magnetic tunnel junctions with combined in-plane and perpendicular polarizers

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Ultrafast spin torque memory based on magnetic tunnel junctions with combined in-plane and perpendicular polarizers