A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ?iterative? harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.

/pdf/digitally-enhanced-software-defined-radio-receiver-robust-to-ictnclarjx.pdf

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a “mixing” and a “sampling” operating region while also covering the design space “in between.” Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.

/pdf/unified-frequency-domain-analysis-of-switched-series-rc-1gn625ruc3.pdf

Unified Frequency-Domain Analysis of Switched-Series- $RC$ Passive Mixers and Samplers

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm2 core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

A 2-mm $^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

Architectural and circuit techniques to integrate the RF front end passive components, namely the SAW filters and duplexers that are traditionally implemented off chip, are presented. Intended for software-defined and cognitive radio platforms, tunable high-Q filters realized by CMOS switches and linear or MOS capacitors allow the integration of highly reconfigurable transceiver front ends that are robust to in-band and out-of-band blockers. Furthermore, duplexer techniques based on electrical balance concepts are introduced to enable highly integrated and programmable radios for full-duplex applications such as 3/4G transceivers. Several case studies are presented that offer highly linear and low-noise transceiver front ends that satisfy the challenging requirements of cellular standards, yet offer considerably lower cost and size compared to the state-of-the-art transceivers available today.

Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial

This paper describes a low-power, low EVM, SAW-less WCDMA transmitter using direct quadrature voltage modulation. The core of the modulator is a passive voltage mixer driven by 25% duty-cycle LO. In comparison with conventional approaches employing Gilbert mixers, the use of a passive voltage mixer results in significantly improved performance in terms of the output noise, linearity, LO leakage, EVM, and the power consumption in the transmitter. Delivering 4 dBm WCDMA output power at 1950 MHz, the transmitter prototype fabricated in a 45 nm CMOS achieves -48 dBc ACLR at 5 MHz offset, -71 dBc ACLR at 10 MHz offset, -54 dBc LO leakage, and 1.36% EVM, while consuming only 26 mW. The measured noise floor at 4 dBm output is -159 dBc/Hz at the frequency offset above 40 MHz, which is sufficient to safeguard the WCDMA RX band, the DCS band, and the GPS band without needing a TX SAW filter. In addition, optimized for low power consumption, over 80 dB gain control under voltage modulation is demonstrated in this paper.

A Low-Power, Low-EVM, SAW-Less WCDMA Transmitter Using Direct Quadrature Voltage Modulation

There has been an increased demand for 3G cell phones that support multiple bands of operation and are backward compatible with the 2G/2.5G standard to provide coverage where 3G networks have not yet been fully deployed. The transceiver design for such a handset becomes complicated with the need for separate transceivers for 3G and 2G/2.5G [1,2] or for multiple inter-stage receive / transmit SAW filters [3]. A single-chip transceiver that operates as a multimode multiband radio and eliminates the inter-stage receive / transmit SAW filters is presented. Figure 6.3.1 shows the block diagram of the transceiver with 7 primary and 4 diversity bands in WCDMA, and quad band in GSM. The transceiver is designed to operate in any of the UTRA bands 1 to 10, with the exception of band 7. It supports HSDPA (Cat 1–12), HSUPA (Cat 1–6), EGPRS (Classes 1–12, 30–39), and compressed mode of EGPRS / WCDMA operation. The transceiver is compliant with 3G DigRF interface 3.09.

Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver paths

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Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver paths