A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S 101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S 102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S 103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S 104, and the nodes of the allocated resource connection graph are shared based on the layout result S 105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

High level synthesis method for semiconductor integrated circuit

A method for converting a hardware description language describing an integrated circuit or software operating thereon to an alternative programming language, such as ANSI C, C++, Java, or other object-oriented programming language, is described. The method provides for the single compilation operations as well as the ability to link multiple compilations to simulate large hardware description language designs. The method of the present invention improves the run time efficiency of the compiled code in a more user-friendly format.

Simulation method and compiler for hardware/software programming

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced.

Method and apparatus for memory abstraction and verification using same

A specific information processing function, which assumes circuit implementation, is described in a programming language, and from this description, an RTL description that can be logic synthesized is automatically generated. A logic circuit generation device includes: a control flow graph generation unit that generates a control flow graph; a control flow degenerate conversion unit that generates a control flow degenerate program by removing all condition branch instructions from the control flow graph; a data flow graph generation unit that generates a data flow graph from the control flow degenerate program; and a logic circuit description output unit that generates logic circuit description indicating a sequential circuit in which a rooted branch of the data flow graph corresponds to the wiring of the logic circuit and a node of the data flow graph corresponds to a computing element of the logic circuit.

Logic circuit generation device and method

The present invention discloses a method and system for computer-aided circuit design for checking the equivalence of data flow graphs by splitting data flow graphs representing finite precision arithmetic circuits into lossless subgraphs representing infinite-precision arithmetic circuits, and edges with information loss. The set of lossless subgraphs generated are leveled, and checked for equivalence as expressions. The edges with information loss are compared by establishing the equivalence of their bit width. The present invention declares data flow graphs as equal, if the respective lossless subgraphs and the bit-width at the corresponding edges with information loss are equal.

Circuit comparison by information loss matching

A method using at least a portion of a control data flow graph (CDFG) which includes multiple control structures in a computer readable storage medium representing at least a portion of a high level design language (HDL) description of an actual or planned logic circuit to evaluate a need for a sequential state element in the portion of the logic circuit comprising producing a graph structure in the storage medium by providing a path origination node in the storage medium; providing a path destination node in the storage medium; producing respective complete paths between the path origination node and the path destination node by separately concatenating each branch of a first control structure of the CDFG with each branch of a second control structure of the CDFG such that a different respective complete path is produced for each possible combination of a respective branch from the first control structure and a respective branch from the second control structure; associating respective complete paths with a respective control statements associated in the CDFG with corresponding branches that have been concatenated with other corresponding branches to produce such respective complete paths; and traversing respective complete paths of the graph information structure to determine whether there is a respective path that is not associated with a respective control statement.

Synthesizing sequential devices from hardware description languages (HDLS)

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Synthesizing sequential devices from hardware description languages (HDLS)