A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Semiconductor devices and methods of fabricating the same

Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Bridge interconnect with air gap in package assembly

A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.

Semiconductor memory device and method of manufacturing the same

According to one embodiment, a process target above a substrate is processed in order to produce a wiring pattern including dense wirings and sparse wirings. Next, a sacrificial film filled between wirings is formed in a region where the dense wirings are formed, and then an insulation film is formed above the substrate. A mask is formed such that a part of the region where the dense wirings are formed is exposed and a region where the sparse wirings are formed is exposed, and the insulation film is etched using the mask. Then, the sacrificial film is removed through a part of the region where the dense wirings are formed. Thereafter, an embedded insulation film is formed above the substrate to fill a gap between adjacent wirings in the region where the sparse wirings are formed.

Method of manufacturing electronic part

In one embodiment, a semiconductor device includes a first insulator, and conductors and second insulators alternately provided on the first insulator. Each second insulator of the second insulators has a first side face adjacent to one of the conductors via a first air gap, a second side face adjacent to one of the conductors via a second air gap, first lower faces in contact with the first insulator, and second lower faces provided above the first insulator via third air gaps.

Semiconductor device and method of manufacturing the same

A method for manufacturing a semiconductor device includes forming first wirings assigned in a first region and second wirings assigned in a second region having a lower wiring density than the first region; covering the first and second wirings with a sacrificial film; reducing a thickness of the sacrificial film until surfaces of the first and second wirings expose; selectively removing the sacrificial film in the second region; depositing a first insulating film on the first and second wirings; and removing the sacrificial film in the first region, so as to form an air gap between the first wirings below the first insulating film.

Method for manufacturing a semiconductor device

According to one embodiment, a method of manufacturing a semiconductor device includes dry-etching a member containing silicon in a first pressure range equal to or more than a first pressure or in a second pressure range equal to or less than a second pressure, wherein the first pressure is obtained by multiplying a saturated pressure by 0.85, the saturated pressure is defined as a pressure under which an etching rate is one of a maximum value or a value obtained by multiplying the maximum value by a predetermined coefficient, and the etching rate is a half value of the maximum value under the second pressure.

Method of manufacturing semiconductor device

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Method for manufacturing a semiconductor device

Method of manufacturing semiconductor device