The demand for lightweight converters with high control performance and low acoustic noise led to an increase in switching frequencies of hard switched two-level low-voltage 3-phase converters over the last years. For high switching frequencies, converter efficiency suffers and can be kept high only by employing cost intensive switch technology such as SiC diodes or CoolMOS switches; therefore, conventional IGBT technology still prevails. In this paper, the alternative of using three-level converters for low-voltage applications is addressed. The performance and the competitiveness of the three-level T-type converter (3LT2C) is analyzed in detail and underlined with a hardware prototype. The 3LT2 C basically combines the positive aspects of the two-level converter such as low conduction losses, small part count and a simple operation principle with the advantages of the three-level converter such as low switching losses and superior output voltage quality. It is, therefore, considered to be a real alternative to two-level converters for certain low-voltage applications.

Design and Implementation of a Highly Efficient Three-Level T-Type Converter for Low-Voltage Applications

In the first part of this paper, three-phase power factor correction (PFC) rectifier topologies with sinusoidal input currents and controlled output voltage are derived from known single-phase PFC rectifier systems and/or passive three-phase diode rectifiers. The systems are classified into hybrid and fully active pulsewidth modulation boost-type or buck-type rectifiers, and their functionality and basic control concepts are briefly described. This facilitates the understanding of the operating principle of three-phase PFC rectifiers starting from single-phase systems, and organizes and completes the knowledge base with a new hybrid three-phase buck-type PFC rectifier topology denominated as Swiss Rectifier. Finally, core topics of future research on three-phase PFC rectifier systems are discussed, such as the analysis of novel hybrid buck-type PFC rectifier topologies, the direct input current control of buck-type systems, and the multi-objective optimization of PFC rectifier systems. The second part of this paper is dedicated to a comparative evaluation of four rectifier systems offering a high potential for industrial applications based on simple and demonstrative performance metrics concerning the semiconductor stresses, the loading and volume of the main passive components, the differential mode and common mode electromagnetic interference noise level, and ultimately the achievable converter efficiency and power density. The results are substantiated with selected examples of hardware prototypes that are optimized for efficiency and/or power density.

The Essence of Three-Phase PFC Rectifier Systems—Part II

Efficient energy conversion in low-voltage applications has gained more attention due to increasing energy costs and environmental issues. Accordingly, three-level converters have been discussed as an alternative to the standard two-level voltage-source converter because they offer an increased efficiency at higher switching frequencies. From a system perspective, the benefits of using three-level converters are not only limited to the converter itself, but there are additional positive impacts on the surrounding such as on the load machine losses or on the electromagnetic interference input filter volume. In this paper, a holistic comparison of advanced three-level topologies against the two-level topology is given. Simple analytical calculations and measurements show the benefits and the optimization potential concerning several aspects, such as the necessary semiconductor chip area, the harmonic losses in the load machine and in filter components, and the volume of passive components.

Comparative Evaluation of Advanced Three-Phase Three-Level Inverter/Converter Topologies Against Two-Level Systems

This paper proposes a fault-tolerant control strategy for a T-type three-level inverter when an open-circuit fault occurs. The proposed method is explained by dividing fault into two cases: the faulty condition of half-bridge switches and neutral-point switches. In case of the open-circuit fault in a neutral-point switch, two methods will be proposed and compared based on thermal analysis and neutral-point voltage oscillation. The reliability of T-type inverter systems is improved considerably by the proposed algorithm when a switch fails. The proposed method does not require any additional components. Simulation and experimental results verify the validity and feasibility of the proposed fault-tolerant control strategy.

Reliability Improvement of a T-Type Three-Level Inverter With Fault-Tolerant Control Strategy

This paper proposes a new diagnosis method of an open-switch fault and fault-tolerant control strategy for T-type three-level inverter systems. The location of the faulty switch can be identified by the average of the normalized phase current and the change of the neutral-point voltage. The proposed fault-tolerant strategy is explained by dividing into two cases: the faulty condition of half-bridge switches and neutral-point switches. The performance of the T-type inverter system improves considerably by the proposed fault-tolerant algorithm when a switch fails. The proposed method does not require additional components and complex calculations. Simulation and experimental results verify the feasibility of the proposed fault diagnosis and fault-tolerant control strategy.

Diagnosis and Tolerant Strategy of an Open-Switch Fault for T-Type Three-Level Inverter Systems

In the low voltage converter range, 3-phase 3-level VSC topologies are not wide spread in industry because of the increased part count and higher costs, although they are more efficient for higher switching frequencies. In this paper an alternative 3-level topology referred to as T-type is presented, which is very high efficient for medium switching frequencies (4–20 kHz). Additionally, it is shown that the total silicon chip area of a 3-level topology can be lower than in a 2-level topology since the losses are distributed over more components leading to only a small increase in the junction temperature. This allows for the design of a chip area and cost optimized 3-level bridge leg module for the mass market.

Comparison of the chip area usage of 2-level and 3-level voltage source converter topologies

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Comparison of the chip area usage of 2-level and 3-level voltage source converter topologies