抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

pdf/training-and-operation-of-an-integrated-neuromorphic-network-2fddhn6pof.pdf

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

The accumulation and extrusion of Ca2+ in the pre- and postsynaptic compartments play a critical role in initiating plastic changes in biological synapses. To emulate this fundamental process in electronic devices, we developed diffusive Ag-in-oxide memristors with a temporal response during and after stimulation similar to that of the synaptic Ca2+ dynamics. In situ high-resolution transmission electron microscopy and nanoparticle dynamics simulations both demonstrate that Ag atoms disperse under electrical bias and regroup spontaneously under zero bias because of interfacial energy minimization, closely resembling synaptic influx and extrusion of Ca2+, respectively. The diffusive memristor and its dynamics enable a direct emulation of both short- and long-term plasticity of biological synapses, representing an advance in hardware implementation of neuromorphic functionalities.

/pdf/memristors-with-diffusive-dynamics-as-synaptic-emulators-for-4j06bmhu3f.pdf

Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing

A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field. This Perspective evaluates the state of the art in memristor-based electronics and explores the future development of such devices in on-chip memory, biologically inspired computing and general-purpose in-memory computing.

The future of electronics based on memristive systems

A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal−oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.

/pdf/nanoscale-memristor-device-as-synapse-in-neuromorphic-1sl2njhdyu.pdf

Nanoscale Memristor Device as Synapse in Neuromorphic Systems

Most hardware neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights two basic learning rules/behavior: winner-take-all (WTA) and spike-timing-dependent plasticity (STDP). It also gives a design example implementing WTA combined with STDP in a position detector. A complementary metal-oxide-semiconductor (CMOS) and a memristor-MOS technology (MMOST) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout were done in 130-nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes area, 55-W max power, and requires a 3-dB SNR. On the other hand, the MMOST design consumes , 15-W max power, and requires a 4.8-dB SNR. There is a potential to improve upon analog computing with the adoption of MMOST designs.

/pdf/cmos-and-memristor-based-neural-network-design-for-position-1th5l7f7i0.pdf

CMOS and Memristor-Based Neural Network Design for Position Detection

The memristor device technology has created waves in the research community and led to the consideration of using the device in multiple avenues. The most likely candidate for early adoption is the nonvolatile memory due to the small cell size (increased scaling potential), increased density as compared to flash, and ability to stack these devices in a crossbar structure. This paper analyzes the feasibility of a memristor memory and introduces an adaptive read, write, and erase method that may be used to realize a more resilient memory system in the face of low yield in the nanotechnology regime. The proposed method is evaluated in simulation program with integrated circuit emphasis (SPICE) and a hand analysis model is extracted to help explain the sources of power and energy consumption. Finally, the power metrics are compared to flash memory technology, and the memristor memory is shown to have an energy per bit consumption about one-tenth that of flash when programming, comparable to flash when erasing, and about one-fourth of flash when reading.

/pdf/self-controlled-writing-and-erasing-in-a-memristor-crossbar-3zsbpdwyia.pdf

Self-Controlled Writing and Erasing in a Memristor Crossbar Memory

The resonant tunneling diode (RTD) has found numerous applications in high-speed digital and analog circuits due to the key advantages associated with its folded back negative differential resistance (NDR) current-voltage (I-V) characteristics as well as its extremely small switching capacitance. Recently, the RTD has also been employed to implement high-speed and compact cellular neural/nonlinear networks (CNNs) by exploiting its quantum tunneling induced nonlinearity and symmetrical I-V characteristics for both positive and negative voltages applied across the anode and cathode terminals of the RTD. This paper proposes an RTD-based CNN architecture and investigates its operation through driving-point-plot analysis, stability and settling time study, and circuit simulation. Full-array simulation of a 128 times 128 RTD-based CNN for several image processing functions is performed using the Quantum Spice simulator designed at the University of Michigan, where the RTD is represented in SPICE simulator by a physics based model derived by solving Schrodinger's and Poisson's equations self-consistently. A comparative study between different CNN implementations reveals that the RTD-based CNN can be designed superior to conventional CMOS technologies in terms of integration density, operating speed, and functionality.

/pdf/tunneling-based-cellular-nonlinear-network-architectures-for-32cr8dozk3.pdf

Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing

Most neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights three basic learning rules - winner-take-all (WTA), spike timing dependent plasticity (STDP), and inhibition of return (IOR). It also gives a design example implementing WTA combined with STDP in a position detector. A CMOS and an MMOST (Memristor-MOS Technology) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout was done in 130 nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes 2.9×10−4cm2 area, 55 µW max power, and requires a 3 dB SNR. On the other hand, the MMOST design consumes 6×10−5cm2, 15 µW max power, and requires a 4.8 dB SNR.

Memristor based STDP learning network for position detection

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