Ibrahim Ban
Intel
35 Papers
503 Citations
Ibrahim Ban is an academic researcher from Intel. The author has contributed to research in topics: Layer (electronics) & Metal gate. The author has an hindex of 13, co-authored 33 publications. Previous affiliations of Ibrahim Ban include Intel Ireland.
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Papers
A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond
Ibrahim Ban,Uygar E. Avci,David L. Kencke,Peter L. D. Chang +3 more
- 17 Jun 2008
TL;DR: A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy.
99
Floating Body Cell with Independently-Controlled Double Gates for High Density Memory
Ibrahim Ban,Uygar E. Avci,Uday Shah,Chris E. Barns,David L. Kencke,Peter L. D. Chang +5 more
- 01 Dec 2006
TL;DR: In this paper, an independently controlled double-gate floating body cell (IDG FBC) was proposed, which eases the scaling constraints of other FBC memory devices proposed to date.
89
3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications
Han Wui Then,Huang Cheng-Ying,B. Krist,Kimin Jun,Kevin Lin,Nidhi Nidhi,T. Michaelos,Mueller Brennen,Rajat Kanti Paul,J. Peck,W. Rachmady,Sansaptak Dasgupta,D. Staines,T. Talukdar,Nicole K. Thomas,Tronic Tristan A,Fischer Paul B,Hafez Walid M,Marko Radosavljevic,P. Agababov,Ibrahim Ban,Robert L. Bristol,Manish Chandhok,Chouksey Siddharth,Brandon Holybee +24 more
- 01 Dec 2019
TL;DR: In this paper, the authors have demonstrated industry's first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric e-mode GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 3D layer transfer.
85
Patent
Floating body memory cell having gates favoring different conductivity type regions
Peter L. D. Chang,Uygar E. Avci,David L. Kencke,Ibrahim Ban +3 more
- 13 Jul 2016
TL;DR: In this article, a method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used, is described.
80
Patent
Independently controlled, double gate nanowire memory cell with self-aligned contacts
Ibrahim Ban,Peter L. D. Chang +1 more
- 28 Dec 2005
TL;DR: In this article, a doubled gate, dynamic storage device and method of fabrication are described, where a back bias gate surrounded three sides of a semiconductor body with a front gate disposed on the remaining surface.
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