Ring-oscillator-based injection-locked frequency divider has merits of compact and low power. The multi-phase injection can improve its locking range, but it needs specific multi-phase inputs, which limits the application of this technique. We present a symmetrical injection circuit to generate the multi-phase injection with only single-phase input. Two injection-locked frequency dividers, with divide-by-3 and divide-by-5 operations respectively, were fabricated in 0.18 μ m CMOS technology to verify the proposed design. The locking range of divide-by-3 and divide-by-5 dividers are 1.6 GHz and 0.9 GHz, with 0.24 and 0.7 mW power consumption in 1 V supply voltage, respectively.

Design of Ring-Oscillator-Based Injection-Locked Frequency Dividers With Single-Phase Inputs

This letter presents a fully differential injection locked frequency divider using coupled dual LC tanks. The proposed injection locked frequency divide-by-2 divider achieves a wide locking range with low injected power levels. The divider, fabricated in 0.18 μm SiGe BiCMOS process achieves a locking range of 3.77 GHz with an injected power as low as -16 dBm, a phase noise of -116 dBc/Hz at 10 kHz offset with an input referred phase noise of -109.7 dBc/Hz at 10 kHz offset at 25 GHz, maximum output power of -2.44 dBm, efficiency of 18.5% and the dc power consumption is 4.8 mW.

/pdf/coupled-dual-lc-tanks-based-ilfd-with-low-injection-power-3ldqsgluho.pdf

Coupled Dual LC Tanks Based ILFD With Low Injection Power and Compact Size

This paper presents divide-by-2 and divide-by-3 injection-locked frequency dividers (ILFDs) using a Darlington cell in a TSMC 0.18- $\mu$ m CMOS process. The Darlington cell has higher transconductance than the traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-2 ILFD to achieve lower power consumption and wide locking range. This work provides an analytic method to choose the injector size for widening the locking range and lowering the power consumption. The measured locking range of the proposed divide-by-2 ILFD is from 20.5 to 22.9 GHz. The measured operation range of the divide-by-3 ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are ${-}{\hbox{138.3}}$ and ${-}140.35$ dBc/Hz at an offset of 1 MHz when the input referred signals have phase noises of ${-}{\hbox{132.54}}$ and ${-}{\hbox{131.5}}$ dBc/Hz, respectively. Meanwhile, both phase noise differences with respect to injection signal are 5.76 and 8.85 dBc, which are close to the theoretical values of 6 and 9.5 dBc. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 $\,\times\,$ 0.75 mm $^{2}$ and 0.77 $\,\times\,$ 0.79 mm $^2$ , respectively.

Designs of K-Band Divide-by-2 and Divide-by-3 Injection-Locked Frequency Divider With Darlington Topology

A new injection-locked frequency divider (ILFD) circuit topology, by combining the strengths of LC type ILFD (LC_ILFD) and ring oscillator type ILFD (RO_ILFD), is proposed to achieve high speed, low power, wide locking range and accurate quadrature output phases. The frequency-division criterion is analyzed and agrees well with simulation results. The phase-locking mechanism is also investigated with emphasis on its resilience to device and circuit mismatches. A prototype is implemented in TSMC 90 nm CMOS to validate the effective locking range of 7.4 GHz (53.4 to 60.8 GHz) with 0 dBm input signal and 5 mW DC power dissipation. The circuit attains the highest figure-of-merit (dividing frequency/power) to date for V-band frequency dividers implemented in deep-scaled CMOS technologies.

A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases

A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than −10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.

A low power, high sensitivity SiGe HBT static frequency divider up to 90 GHz for millimeter-wave application

A 20–30 GHz divide-by-3 ring-based injection locked frequency divider (ILFD) using NMOS loads for a wide locking range has been developed in a commercial 0.13-μm Si RFCMOS technology.The ILFD shows a locking range up to 7.5 GHz (20.8−28.3 GHz, 30.5%) and operation range of 10 GHz (20.8–30.8 GHz, 38.8%) with DC power consumption of 13 mW and a 1.5 V supply voltage. The fabricated circuit occupies only 0.008 mm2 core area. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:389–841, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25883

A 20–30 GHz divide‐by‐3 ring‐oscillator‐based injection locked frequency divider with a wide locking range

In this work, a single-ended divide-by-2 injection locked frequency divider with inductive feedback is presented. The frequency divider, fabricated in a commercial 0.18 μm SiGe HBT technology, showed a measured locking range of 126.9–141.5 GHz (14.7 GHz) and an operating range of 126.9–150.0 GHz (23.1 GHz) with bias adjustment. The DC power consumption of the ILFD core was 6.9 mW and that of the output buffer was 13.5 mW.

A 140 GHz single-ended injection locked frequency divider with inductive feedback in SiGe HBT technology

An injection-locked frequency divider (ILFD) with an inductive feedback for enhanced locking range has been developed in a commercial 0.13 μm Si RFCMOS technology and compared with a conventional ILFD. The proposed ILFD showed a significant improvement in the locking range over the conventional ILFD, operating at a frequency range of 43.60-48.95 GHz. The dc power consumption of the ILFD was 0.58 mW with a supply voltage of 1.2 V for the divider core.

A $Q$ -Band Injection-Locked Frequency Divider With Inductive Feedback for a Locking Range Enhancement

Presented is a D-band divide-by-3 injection-locked frequency divider (ILFD) based on a ring oscillator in a 0.18 µm SiGe BiCMOS technology. The ILFD exhibits a locking range of 7.9 GHz (132.5–140.4 GHz) at an input signal power of −2 dBm, dissipating a total DC power of 71.2 mW. The ILFD core occupies an area of 0.0021 mm2.

SiGe 140 GHz ring-oscillator-based injection-locked frequency divider

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90- nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm × 0.69 mm including the DC and RF pads.

A 90-nm CMOS 144 GHz Injection Locked Frequency Divider with Inductive Feedback

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