In the quest to study the fundamental nature of matter and the universe, high-energy physics (HEP) experiments often operate in extreme conditions that lie well outside the standard operating range of integrated circuits (ICs). Two prominent examples of such extreme environments are 1) the irradiation levels experienced at high luminosity colliders and 2) operation at cryogenic temperatures [1]. Cryogenic electronics is a broad term that encompasses circuits operating at temperatures below the standard operating limit (m55 dC in the case of military grade electronics), all of the way down to millikelvin, as in the case of superconducting circuits. Cryogenic circuits have a long history [2] and have found applications in a broad spectrum of applications, such as infrared focal plane arrays, positron emission tomography, and quantum science. While CMOS circuits have been reliably operated at deep-cryogenic temperatures (l 4.2 K), this article focuses on applications down to liquid nitrogen (77 K) and provides an overview of the design considerations, benefits, and unique challenges pertaining to cryogenic CMOS ICs for large HEP experiments.

Cryogenic Electronics Development for High-Energy Physics: An Overview of Design Considerations, Benefits, and Unique Challenges

In this paper we present the general features of cryogenic (or “cold”) electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. “Cold” in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN2 (77 K). The paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper. 

Cryogenic electronics for noble liquid neutrino detectors

We propose a simplified and efficient apparatus for a cosmic microwave background (CMB) detector employing a cryogenic controller IC for a large TES (Transition Edge Sensor) array. The proposed apparatus significantly improves the passive heat load by reducing the number of wires originating from the room temperature electronics. In the current proposal, the cryogenic controller handles two critical circuit functions, namely the row multiplexer and the bias DAC. Those circuits can be scaled to handle a large number of channels required for the next generation of CMB telescopes with 500 k detectors. As a step towards realizing such a solution, the aforementioned circuits are designed using a low power and low noise topology and simulated to verify system specification compliance. The circuit design is fabricated in Global-Foundries 22-nm FD-SOI CMOS process and is awaiting lab measurements.

Towards A Fully Integrated TES Controller Operating at 4K Temperature

CRYO is a charge read-out ASIC aimed for noble liquid Time Projection Chamber (TPC) experiments. It implements a system-on-chip (SoC) architecture with minimal number of I/Os making it an attractive solution for neutrino experiments such as DUNE (far detector) and nEXO. Two different variants of CRYO ASIC have been designed to meet the requirements of the experiments. The version for DUNE has been reported previously by immersing the ASIC in LN2 to be close to LAr temperature (i.e., 87 K). This contribution, on the other hand, focuses on the test and characterization of the nEXO variant, an improved version optimized to operate at 160 K and with the front-end (FE) section tailored for the equivalent capacitance of the LXe detector (i.e., 40 pF). The small size of the ASIC (7 mm x 9 mm) and the absence of packaging bring an additional benefit in terms of radioactivity load, which is a critical requirement in nEXO for rare events such as neutrinoless double beta (0 νββ) decay. Similar to the DUNE version, the nEXO variant is fabricated in a 130 nm CMOS process and works with a single supply voltage. We present preliminary results obtained in cold gas using LN2 to emulate the LXe environment (i.e., 160 K).

CRYO: A System-on-Chip for Charge Readout in the nEXO Experiment

This work presents the implementation of the digital read-out architecture of a System-On-Chip (SoC) optimized for Time Projection Chamber (TPC) detectors used in neutrino science. The CRYO ASIC works at cryogenic temperatures and performs signal pre-amplification, waveform digitization and channel multiplexing with minimum number of I/Os. The digital back-end is optimized to work with cryogenic liquids (LXe, 160 K and LAr, 87 K) providing data throughput up to 1 Gbps and can be programmed to maintain signal integrity up to 25 m cable length. Implemented in 130 nm CMOS process, the back-end architecture consists of a digital multiplexer, a custom 12b/14b encoder, a data serializer, and LVDS (Low-Voltage Differential Signaling) drivers with pre-emphasis enhancing techniques. The simulated output jitter of transmitter is 29.3 ps, peak-to-peak (0.15 UI) driving a 25 m cable at 1 Gbps data rate.

Read-Out Architecture of CRYO System-on-Chip ASIC for Noble Liquid TPC Detectors

A sampling technique for X-ray detectors is presented, which performs a two channel single-ended-to-differential sampling, and buffers the sampled signals serially to the incremental Sigma Delta ADC. This sampling technique maximizes the readout speed of the X-ray detectors, while allowing the ADC to sample the input signal multiple times for reduced thermal noise and higher resolution. The sampler is implemented in 0.25 µm CMOS technology, as a part of a mixed signal processing backend for the pixel signal, consists of buffering, ADC conversion and readout circuits. Measured performance shows a high resolution of >77 dB SNR at 3.3 Kfps, which emphasizes the speed advantage and high linearity of the proposed approach.

Single-Ended-to-Differential Sampling Technique for Sigma Delta ADCs in X-Ray Detectors

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Hussein Ali

Author Tools

Chat about Author

Papers

Read-Out Architecture of CRYO System-on-Chip ASIC for Noble Liquid TPC Detectors

Single-Ended-to-Differential Sampling Technique for Sigma Delta ADCs in X-Ray Detectors