Introduction System-on-Chip Integration and Its Challenges SoC to Network-on-Chip: A Paradigm Shift Research Issues in NoC Development Existing NoC Examples Summary References Interconnection Networks in Network-on-Chip Introduction Network Topologies Switching Techniques Routing Strategies Flow Control Protocol Quality-of-Service Support NI Module Summary References Architecture Design of Network-on-Chip Introduction Switching Techniques and Packet Format Asynchronous FIFO Design GALS Style of Communication Wormhole Router Architecture Design VC Router Architecture Design Adaptive Router Architecture Design Summary References Evaluation of Network-on-Chip Architectures Evaluation Methodologies of NoC Traffic Modeling Selection of Channel Width and Flit Size Simulation Results and Analysis of MoT Network with WH Router Impact of FIFO Size and Placement in Energy and Performance of a Network Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic Simulation Results and Analysis of MoT Network with Virtual Channel Router Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router Limitations of Tree-Based Topologies Summary References Application Mapping on Network-on-Chip Introduction Mapping Problem ILP Formulation Constructive Heuristics for Application Mapping Constructive Heuristics with Iterative Improvement Mapping Using Discrete PSO Summary References Low-Power Techniques for Network-on-Chip Introduction Standard Low-Power Methods for NoC Routers Standard Low-Power Methods for NoC Links System-Level Power Reduction Summary References Signal Integrity and Reliability of Network-on-Chip Introduction Sources of Faults in NoC Fabric Permanent Fault Controlling Techniques Transient Fault Controlling Techniques Unified Coding Framework Energy and Reliability Trade-Off in Coding Technique Summary References Testing of Network-on- Chip Architectures Introduction Testing Communication Fabric Testing Cores Summary References Application-Specific Network-on-Chip Synthesis Introduction ASNoC Synthesis Problem Literature Survey System-Level Floorplanning Custom Interconnection Topology and Route Generation ASNoC Synthesis with Flexible Router Placement Summary References Reconfigurable Network-on-Chip Design Introduction Literature Review Local Reconfiguration Approach Topology Reconfiguration Link Reconfiguration Summary References Three-Dimensional Integration of Network-on-Chip Introduction 3-D Integration: Pros and Cons Design and Evaluation of 3-D NoC Architecture Summary References Conclusions and Future Trends Conclusions Future Trends Comparison between Alternatives References Index

Network-on-Chip: The Next Generation of System-on-Chip Integration

The growing demand for enhanced batteries with higher energy density and safety is pushing lithium-ion battery technology towards solid-state batteries. Replacing the liquid with a solid electrolyte significantly improves safety by removing the possibility of leaking flammable organic solvents. Solid electrolytes also enable the use of lithium metal as anode material to obtain battery cells with higher energy density. This review summarizes the classification of all three state-of-the-art solid electrolyte types (inorganic, polymer and composite solid electrolytes) and their governing lithium ion transport mechanisms. Nevertheless, to make solid-state batteries applicable, improvements in ionic conductivity of the solid electrolyte, low electrode-electrolyte interfacial resistance and high compatibility of the solid electrolyte with the electrodes are required. This review paper discusses improvement strategies for solid electrolytes to achieve high ionic conductivity, good flexibility, and high electrode compatibility. Enhanced ionic conductivity can be obtained by suppressing the polymer phase's crystallization (e.g., copolymerization, inorganic fillers, adjusting polymer matrix) and optimizing the physicochemical parameters and the surface of the inorganic phase. Interfacial stability can be improved by using multilayered electrolytes or applying coatings and passivation layers on electrolyte or electrode particles. 

Advances in inorganic, polymer and composite electrolytes: Mechanisms of Lithium-ion transport and pathways to enhanced performance

Solid-state lithium-ion batteries with composite polymer electrolytes are considered to be one of the most apparent technology to lead in the world of batteries. The primary upside of such batteries is their addressed safety issues followed by good flexibility along with mechanical strength and improved interfacial conditions. Among various polymers, poly (vinylidene fluoride-hexafluoropropylene) (PVDF-HFP) has exhibited to be potential enough to easily dissociate lithium salts as it is enriched with strong electron withdrawing groups. Along the years, researchers have introduced various methods by which the ionic conductivity and the overall performance have effectively improved. Hence, in this review we briefly discuss the recent progress and major contributions of several passive and active fillers in composite polymer electrolytes (CPEs) and how they consequently impact the overall cell performance. The unique mechanisms as well as effects of fillers with respect to their dimension, optimal quantity and type and how they can overcome the limitations of conventional solid polymer electrolytes (SPEs) are detailed here. Mostly the factors affecting the ionic conductivity and overall cell performance in PVDF-HFP based CPEs are intensively reviewed. Finally, we evaluated the improvisions made to diminish the electrode-electrolyte interfacial resistance which contributes a major role in all solid-state batteries. 

Review on composite polymer electrolyte using PVDF-HFP for solid-state lithium-ion battery

This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The area overhead for this local reconfiguration has been shown to be very small. We have also presented the strategy to map the cores of an application set onto this architecture. This has been achieved via a two-phase procedure. In the first phase, the cores of the combined application set are mapped tentatively to individual routers, minimizing the communication cost. In the second phase, for each application, positions of individual cores are finalized. A core gets attached to any neighbor of its tentative allocation. We have proposed Integer Linear Programming (ILP) formulation of both the phases. Since ILP takes large amount of CPU time, we have also formulated a Particle Swarm Optimization (PSO)-based solution for the two phases. A heuristic approach has also been developed for the reconfiguration. Comparison of communication cost, latency and network energy have been carried out for the applications, before and after reconfiguration. It shows significant improvement in performance via reconfiguration.

Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration

Abstract The use of all‐solid‐state lithium metal batteries (ASSLMBs) has garnered significant attention as a promising solution for advanced energy storage systems. By employing non‐flammable solid electrolytes in ASSLMBs, their safety profile is enhanced, and the use of lithium metal as the anode allows for higher energy density compared to traditional lithium‐ion batteries. To fully realize the potential of ASSLMBs, solid‐state electrolytes (SSEs) must meet several requirements. These include high ionic conductivity and Li + transference number, smooth interfacial contact between SSEs and electrodes, low manufacturing cost, excellent electrochemical stability, and effective suppression of dendrite formation. This paper delves into the essential requirements of SSEs to enable the successful implementation of ASSLMBs. Additionally, the representative state‐of‐the‐art examples of SSEs developed in the past 5 years, showcasing the latest advancements in SSE materials and highlighting their unique properties are discussed. Finally, the paper provides an outlook on achieving balanced and improved SSEs for ASSLMBs, addressing failure mechanisms and solutions, highlighting critical challenges such as the reversibility of Li plating/stripping and thermal runaway, advanced characterization techniques, composite SSEs, computational studies, and potential and challenges of ASS lithium–sulfur and lithium–oxygen batteries. With this consideration, balanced and improved SSEs for ASSLMBs can be realized. 

Solid‐State Electrolytes for Lithium Metal Batteries: State‐of‐the‐Art and Perspectives

Three-Dimensional Llzo/Pvdf-Hfp Fiber Network-Enhanced Ultrathin Composite Solid Electrolyte Membrane for Dendrite-Free Solid-State Lithium Metal Batteries

With the challenge that a larger number of cores will be integrated on one single chip, Network-on-Chip (NoC) has been the popular solution gradually. And recently, researchers have focused on improving the performance of NoC to achieve well-performed chips. In this paper, we will propose a configuring algorithm based on one reconfigurable NoC architecture to design application-specific NoC. The reconfigurable NoC architecture decreases the design complexity and makes NoC design more flexible comparing to the topology-generation-floorplanning scheme and mapping scheme respectively. Besides, our configuring algorithm aims at optimized networks with better performance. For one specific application, we can choose the reconfigurable NoC architecture with suitable size and configure it according to the communication relationship to make sure that the final network is optimized. A cycle-accurate simulator is used to carry out simulations for three networks designed by our scheme and two other methods for the same application under the same environment. The results turn out that our network performs better.

Configuring algorithm for reconfigurable Network-on-Chip architecture

The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signal TSVs. What’s more, the peak temperature is limited by placing IP cores with high power on the layer close to the heat sink. Experimental results indicate that the number of signal TSVs is decreased and that tradeoffs can be made between the number of signal TSVs and peak temperature.

3D Networks-on-Chip mapping targeting minimum signal TSVs

Preparation and Versatility of a Novel Functional Biomedical Polyurethane Material

Three-dimensional network-on-chip (3D NoC) applying Through-Silicon-Vias (TSVs) is the most promising process in achieving higher network bandwidth, lower latency and lower power consumption. Unfortunately, the fabrication process of TSV connection has not matured yet, which results in poor vertical links yield thus the yield of 3D NoC decreases sharply with the growth in the number of TSVs. To ensure the yield of the 3D NoC, in this paper we propose a hybrid vertical interconnect scheme which minimizes the number of TSV by sharing vertical links through vertical routers.

http://ieeexplore.ieee.org/iel7/6959195/6967050/06967232.pdf

A hybrid vertical interconnect for three-dimensional network-on-chip

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Hui Ding

Author Tools

Chat about Author

Papers

Three-Dimensional Llzo/Pvdf-Hfp Fiber Network-Enhanced Ultrathin Composite Solid Electrolyte Membrane for Dendrite-Free Solid-State Lithium Metal Batteries

Configuring algorithm for reconfigurable Network-on-Chip architecture

3D Networks-on-Chip mapping targeting minimum signal TSVs

Preparation and Versatility of a Novel Functional Biomedical Polyurethane Material

A hybrid vertical interconnect for three-dimensional network-on-chip