13 Papers
119 Citations
Hu Xu is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Clock skew & Skew. The author has an hindex of 6, co-authored 13 publications. Previous affiliations of Hu Xu include Peking University.
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Papers
Analytical heat transfer model for thermal through-silicon vias
Hu Xu,Vasilis F. Pavlidis,Giovanni De Micheli +2 more
- 14 Mar 2011
TL;DR: Two resistive networks are utilized to model the physical behavior of TTSVs and are used for the thermal analysis of a 3-D DRAM-μP system where the conventional model is shown to considerably overestimate the temperature of the system.
The combined effect of process variations and power supply noise on clock skew and jitter
Hu Xu,Vasilis F. Pavlidis,Wayne Burleson,Giovanni De Micheli +3 more
- 19 Mar 2012
TL;DR: In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations, and a statistical model of skitter, which consists of skew and jitter is proposed.
Process-induced skew variation for scaled 2-D and 3-D ICs
Hu Xu,Vasilis F. Pavlidis,Giovanni De Micheli +2 more
- 13 Jun 2010
TL;DR: 3-D integration is shown to be an alternative to reduce skew variation without the need of aggressive technology scaling and a comparison between these two design paradigms is offered such that the appropriate technology node and number of planes are selected to produce a low clock skew variation and high operating frequency.
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise
TL;DR: A statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced and a set of guidelines are presented to decrease skitter in3-D ICs.
Effect of process variations in 3D global clock distribution networks
TL;DR: Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies, and a multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew.