Horácio C. Neto
Instituto Superior Técnico
106 Papers
611 Citations
Horácio C. Neto is an academic researcher from Instituto Superior Técnico. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 16, co-authored 101 publications. Previous affiliations of Horácio C. Neto include INESC-ID & University of Lisbon.
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Papers
Trends of CPU, GPU and FPGA for high-performance computing
Mário P. Véstias,Horácio C. Neto +1 more
- 20 Oct 2014
TL;DR: In this article, the authors compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains, showing that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from highperformance computing with intensive floating-point calculations.
101
Macro-based hardware compilation of Java/sup TM/ bytecodes into a dynamic reconfigurable computing system
João M. P. Cardoso,Horácio C. Neto +1 more
- 21 Apr 1999
TL;DR: This paper presents a new approach to synthesize to reconfigurable hardware (HW) user-specified regions of a program, under the assumption of "virtual HW" support, which exploits the temporal partitions at the behavior level, resolves memory access conflicts, and generates the VHDL descriptions at register-transfer level that will be mapped into the reconfigured HW devices.
98
A Full Featured Configurable Accelerator for Object Detection With YOLO
Daniel Pestana,Pedro R. Miranda,João D. Lopes,Rui Policarpo Duarte,Mário P. Véstias,Horácio C. Neto,Jose T. de Sousa +6 more
TL;DR: In this paper, a configurable and scalable core for real-time object detection and classification based on YOLO targeting embedded platforms has been proposed, which accelerates the execution of all the algorithm steps, including preprocessing, model inference and post-processing.
Compilation for FPGA-based reconfigurable hardware
TL;DR: This paper provides techniques for compiling software programs into reconfigurable hardware which offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems.
60
Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation
Paulo Flores,José Carlos Costa,Horácio C. Neto,José Monteiro,Joao Marques-Silva +4 more
- 10 Jan 1999
TL;DR: This paper develops an optimization model and describes an efficient algorithm for reordering pattern sequences in the presence of don't cares and preliminary experimental results amply confirm that the resulting power savings due to pattern sequence reordering usingDon't cares can be significant.