Sensor nodes massively deployed in Internet of Things are subject to physical capture, hardware tampering, device cloning, and unauthorized device alteration. This paper presented a novel ring oscillator PUF (Physical Unclonable Function) circuit exploiting the process variation of both CMOS devices and TSVs (Through Silicon Vias) available on TSV-based 3D stacking sensor nodes, for secure data generation resistant to physical attacks. As far as we know from the literature, this is the first work on TSV-based 3D PUF circuits. Simulation results based on a 0.18-μm CMOS technology and a 5.2-μm via-last TSV technology show that the proposed 3D PUF circuit has stronger uniqueness and reproducibility in PUF behavior.

TSV-based PUF circuit for 3DIC sensor nodes in IoT applications

During the last few years critical advancements in Wireless Sensor Networks (WSNs) have highlighted respective platforms as a prominent technology able to tackle various challenges posed by Smart-City application scenarios. However, a critical area that has not been adequately taken into consideration concerns security provision necessity in conjunction to its impact on real WSN platform communication efficiency. Consequently, specific practices must be defined in alignment with, up to date, regulations and legislation. In this paper, a two-fold contribution is made. On one hand, a comprehensive study is presented focusing on practices that a real WSN must follow so as to comply with the current security and privacy regulations and legislations. On the other hand, a system level evaluation is presented emphasizing on the effect of security algorithms utilization upon the behavior and performance of a prominent real WSN environment. This evaluation is based on experimentations using a prominent WSN platform enabling algorithms offering high level security features while varying a wide range of critical network parameters.

Security data management process and its impact on smart cities' wireless sensor networks

This paper introduces test solutions for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promising of being a very cost effective solution to achieve “More than Moore's law” for mobile devices — more so than 3D integrated circuits (3DIC). InFO WLCSP has its own unique test challenges and it is important to have high-quality screen methodology for severe defects and potential reliablity failures. In this paper we propose novel solutions that leads to fast and reliable tests for InFO WLCSP packages. We will show results on some industrial cases to validate our claims.

Fan-out wafer level chip scale package testing

Recently, the technology of wireless sensor networks (WSNs) experiences a growing use in home automation or advanced industry infrastructure applications. Despite a strong interest of industries in this technology, key issues like miniaturization and security of WSN nodes has not been solved yet. State-of-the-art WSN nodes do not provide credible security nor satisfying configurability and miniaturized implementations. This publication deals with these limitations and presents a WSN node that provides security, configurability, and a miniaturized design. To show the sensor node feasibility, the WSN node is implemented within a smart home demonstrator. Additionally, a miniaturized pre-study WSN node design is presented using the novel embedded wafer level ball grid array (eWLB) packaging technology. Furthermore, an eWLB based WSN node design is proposed that further miniaturize the presented WSN node.

A secure miniaturized wireless sensor node for a smart home demonstrator

This paper introduces a high quality screening methodology, using Integrated Passive Device (IPD) as an example device, which has the capability to increase power integrity of Integrated Fan Out Wafer Level Chip Scale Package (InFO WLCSP). InFO WLCSP is a more cost effective solution to achieve “More than Moore’s law” for mobile devices than 3D integrated circuits (3DIC). Ultra-thin IPD with high capacitance densityis capable to further shrinking InFO package dimensions and boosting its performance. Although the cost percentage of an IPD in the whole InFO package is negligible, a defective IPD can cause the whole InFO package malfunctioned. Traditional test methods such as good die in a bad cluster (GDBC) and dynamic part averaging testing (DPAT) are used screening IPD devices, however it is insufficient for high quality screen standards. In this paper, we propose a novel methodology that leads to an effective screening method to guarantee high quality and reliable IPD devices for InFO packages. We will show results on some industrial cases to validate our claims.

Smart GDBC Screening for High Quality IPD

In this paper, an innovative design of a miniaturized heterogeneous 3DIC-based wireless sensor node (WSN) is proposed. The design contains stacks of radio frequency (RF) die, mixed-signal die, digital die, and integrated antenna die using the through silicon via (TSV) technology. Significant enhancements to the existing 2D design and verification flow are developed to solve the critical concerns of heterogeneous 3DIC integration, including the block-level partitioning, TSV macro design, the TSV-related modeling and characterization, and physical verification. Solutions are proposed to minimize the electromagnetic interference (EMI) effects between the IC and the antenna. The size of the proposed 3DIC is only 66% as compared to a similar 2D implementation, permitting miniaturization of the complete WSN system.

A miniaturized heterogeneous wireless sensor node in 3DIC

3DIC's, the flagship for the “More than Moore Law” movement are already an integral part of the Semiconductor and Manufacturing industry and lot of investigations are going on within different sectors of the industry to efficiently fabricate 3DIC's. If you peep deep into the design process, everyone is trying to make it upward compatible with the 2D design for effective reusability. The methodology to design and verify the 3DIC involves a collaboration of different people from EDA, CAD, Physical design, Fabrication, TSV and Modeling departments. Different aspects need to be considered for the 3DIC apart from the miniaturization and the resulting space, cost & signal loss savings. The considerations include Power & clock Distribution, Thermal analysis, EMI, ESD protection scheme etc. This paper focuses on the physical design process steps carried out to develop a 3DIC Wireless Transceiver and it throws light into some of the process intricacies which are faced while carrying out the design and verification of such an IC stacking.

Physical design exploration of 3DIC wireless transceiver using through-si-vias

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A miniaturized heterogeneous wireless sensor node in 3DIC

Physical design exploration of 3DIC wireless transceiver using through-si-vias