Internet of Things (IoT) is an ecosystem of connected edge devices that are accessible through the internet. Recent research focusses on adding more smartness and intelligence to these edge devices...

Low-Cost AES-128 Implementation for Edge Devices in IoT Applications

With the increase in computation and data storage in cloud servers, the need for a dedicated hardware accelerator for encryption is arising in order to reduce the processor job. High-throughput and resource-optimized implementation of 128-bit Advanced Encryption Standard (AES 128-bit), which can be used as an accelerator, is presented in this article. Memory partitioning is done in order to assign multiple ports for parallel data access. After the algorithm is pipelined and unrolled at each operation on the basis of the analyzed latency and initiation interval of different operations, for each critical path delays, a new multistage single initiation interval sub-pipelined architecture is proposed to make the initiation interval to one for lowest path delay. As a result, all operations in AES can be initiated within one clock cycle and can accept input in every clock cycle. The proposed method when simulated, synthesized, and implemented on the latest XC7VX690T device gives a throughput of 104.06 Gbps at a maximum frequency of 813 MHz and 1.23-ns path delay. The resource utilization is lower when compared with other counterparts. The proposed system gives 30.74 Mbps efficiency on XC5VLX85 device, which is 27.13% more than the best efficiency reported in a previous work.

AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

New byte-addressable non-volatile memory (BNVM) technologies such as phase change memory (PCM) enable the construction of systems with large persistent memories, improving reliability and potentially reducing power consumption. However, BNVM technologies only support a limited number of lifetime writes per cell and consume most of their power when flipping a bit’s state during a write; thus, PCM controllers only rewrite a cell’s contents when the cell’s value has changed. Prior research has assumed that reducing the number of words written is a good proxy for reducing the number of bits modified, but a recent study has suggested that this assumption may not be valid. Our research confirms that approaches with the fewest writes often have more bit flips than those optimized to reduce bit flipping. To test the effectiveness of bit flip reduction, we built a framework that uses the number of bits flipped over time as the measure of “goodness” and modified a cycle-accurate simulator to count bits flipped during program execution. We implemented several modifications to common data structures designed to reduce power consumption and increase memory lifetime by reducing the number of bits modified by operations on several data structures: linked lists, hash tables, and red-black trees. We were able to reduce the number of bits flipped by up to 3.56× over standard implementations of the same data structures with negligible overhead. We measured the number of bits flipped by memory allocation and stack frame saves and found that careful data placement in the stack can reduce bit flips significantly. These changes require no hardware modifications and neither significantly reduce performance nor increase code complexity, making them attractive for designing systems optimized for BNVM.

/pdf/optimizing-systems-for-byte-addressable-nvm-by-reducing-bit-3ket1l13ll.pdf

Optimizing Systems for Byte-Addressable NVM by Reducing Bit Flipping.

The applications and uses of embedded systems is increasingly pervasive. Mission and safety critical systems relying on embedded systems pose specific challenges. Embedded systems is a multi-disciplinary domain, involving both hardware and software. Systems need to be designed in a holistic manner so that they are able to provide the desired reliability and minimise unnecessary complexity. The large problem landscape means that there is no one solution that fits all applications of embedded systems. With the primary focus of these mission and safety critical systems being functionality and reliability, there can be conflicts with business needs, and this can introduce pressures to reduce cost at the expense of reliability and functionality. This paper examines the challenges faced by battery powered systems, and then explores at more general problems, and several real-world embedded systems.

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2017.1409813

Review of battery powered embedded systems design for mission-critical low-power applications

The advent of byte-addressable non-volatile memory technologies such as phase change memory (PCM) has spurred a flurry of research on topics including consistency and durability of data structures across power failures and optimizing systems for the low-latency nature of these technologies, while typically aiming to increase lifetime and reduce power consumption by reducing the number of writes to the non-volatile memory. However, in technologies such as PCM, it is bit flips that consume power and wear out cells, not writes. Thus, PCM controllers do not rewrite cells unless the cell changes value. However, this crucial optimization, reducing the number of bits flipped, has not been sufficiently explored for the rest of the hardware and software stack. We develop a framework for using the number of bit flips as the measure of "goodness" for a range of hardware and software techniques. We also introduce several simple and straightforward modifications to existing data structures that can reduce the number of bit flips over time, and profile use cases in which the approach with the fewest writes does not also minimize bit flips. Based on these findings, we discuss potential approaches that can further minimize bit flips, better optimizing hardware and software for non-volatile memory technologies such as PCM.

/pdf/designing-data-structures-to-minimize-bit-flips-on-nvm-58msp386nl.pdf

Designing Data Structures to Minimize Bit Flips on NVM

Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on However, PCM is still restricted for use as main memory because of its limited write endurance There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead CABS achieved up to 485% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits Moreover, CABS obtained approximately 97% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them Also, CABS reduced about 54% of write dynamic energy compared to DCW Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 321%

Content-Aware Bit Shuffling for Maximizing PCM Endurance

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCC were on average 8% and 7% lower than those of LLVM, respectively.

http://koreascience.or.kr:80/article/JAKO201424635080447.pdf

Performance Comparison between LLVM and GCC Compilers for the AE32000 Embedded Processor

Voltage scaling is known to be an efficient way of saving power and energy within a system, and large caches such as LLCs are good candidates for voltage scaling considering their constantly increasing size. However, the VCCMIN problem, in which the lower bound of scalable voltage is limited by process variation, has made it difficult to exploit the benefits of voltage scaling. Lowering VCCMIN incurs multibit faults, which cannot be efficiently resolved by current technologies due to their high complexity and power consumption. We overcame the limitation by exploiting the data redundancy of memory hierarchy. For example, cache coherence states and several layers of cache organization naturally expose the existence of redundancy within cache blocks. If blocks have redundant copies, their VCCMIN can be lowered; although more faults can occur in the blocks, they can be efficiently detected by simple error detection codes and recovered by reloading the redundant copies. Our scheme requires only minor modifications to the existing cache design. We verified our proposal on a cycle accurate simulator with SPLASH-2 and PARSEC benchmark suites and found that the VCCMIN of a 2MB L2 cache can be further lowered by 0.1V in 32nm technology with negligible degradation in performance. As a result, we could achieve 15.6p of reduction in dynamic power and 15.4p of reduction in static power compared to the previous minimum power.

Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy

In embedded systems, code size and dynamic instruction count are important performance indicators of power consumption and execution time. However, the use of different compilers may result in large different performance values even if a target machine is the same. So, the compiler selection in the system development is very important. In this paper, we compare the performances of two popular compilers, GCC and LLVM in perspective of the code size and the dynamic instruction count for the EISC embedded processor. Our comparison shows that LLVM is good at optimizing calculation intensive benchmarks, and GCC performs register allocation and jump optimization better. Overall, the GCC compiler shows better performance in most EEMBC benchmarks about 18% on average in terms of dynamic instruction. Also, the compiled code size by GCC is smaller than that of LLVM by 4% on average.

Performance comparison of GCC and LLVM on the EISC processor

A method for extending the lifetime of a resistive change memory includes generating data and hash candidates by shuffling bit positions of write data with the hash candidates in response to a write request for the resistive change memory, calculating Hamming distances of the generated data and hash candidates from stored data and a stored hash, matching stuck data at a predetermined bit in the resistive change memory with the generated data and hash candidates when the stuck data is at the predetermined bit, and excluding mismatched data and hash candidates that are mismatched with the stuck data among the generated data and hash candidates, finding a data and hash candidate with the shortest Hamming distance among the matched data and hash candidates, and choosing the found data and hash candidate as an encoded data and hash, and storing the encoded data and hash in the resistive change memory.

Method for extending lifetime of resistive change memory and data storage system using the same

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