Hiroaki Ueno
Hiroshima University
44 Papers
275 Citations
Hiroaki Ueno is an academic researcher from Hiroshima University. The author has contributed to research in topics: MOSFET & Electron mobility. The author has an hindex of 9, co-authored 44 publications. Previous affiliations of Hiroaki Ueno include Panasonic & Osaka University.
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Papers
Patent
Transistor and method for operating the same
Daisuke Ueda,Tsuyoshi Tanaka,Yasuhiro Uemoto,Tetsuzo Ueda,Manabu Yanagihara,Masahiro Hikita,Hiroaki Ueno +6 more
- 27 Jun 2006
TL;DR: In this article, holes are injected into a channel to increase a current flowing in the channel by applying a positive voltage to the p-type control layer 105, which is injected to increase the current flow in a channel.
68
HiSIM: a MOSFET model for circuit simulation connecting circuit performance with technology
Mitiko Miura-Mattausch,Hiroaki Ueno,M. Tanaka,Hans Jurgen Mattausch,S. Kumashiro,T. Yamaguchi,K. Yamashita,N. Nakayama +7 more
- 08 Dec 2002
TL;DR: HiSIM (Hiroshima-University STARC IGFET Model), aiming to fulfil both requirements, is based on an iterative surface-potential determination in 2D device simulators, thus simplifying modeling procedure and allowing large-scale circuit simulation with 0.1 /spl mu/m-MOSFET technologies.
35
Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation
Hiroaki Ueno,D. Kitamaru,K. Morikawa,M. Tanaka,Mitiko Miura-Mattausch,Hans Jurgen Mattausch,S. Kumashiro,T. Yamaguchi,K. Yamashita,N. Nakayama +9 more
TL;DR: In this paper, a threshold voltage (V/sub th/ versus gate-length (L/sub gate/) model was developed for pocket-implant technology, which extracts the threshold condition from the entire mobile charge concentration in the channel with only five additional parameters.
22
Non-quasi-static model for MOSFET based on carrier-transit delay
N. Nakayama,Dondee Navarro,M. Tanaka,Hiroaki Ueno,Mitiko Miura-Mattausch,Hans Jurgen Mattausch,T. Ohguro,S. Kumashiro,M. Taguchi,T. Kage,S. Miyamoto +10 more
TL;DR: A non-quasi-static MOSFET model for circuit simulation, which is based on the carrier-transit delay responsible for the channel formation during switching on, has been developed and good agreement of transient drain current with 2D simulation results was confirmed.
21
Patent
Simulation model for design of semiconductor device, thermal drain noise analysis method, simulation method, and simulation apparatus
Mitiko Miura,Hiroaki Ueno,Satoshi Kure Hosokawa +2 more
- 13 Dec 2004
TL;DR: In this article, a drain current I ds of a MOSFET is calculated and substituted into a relational expression for a thermal drain current noise spectrum density obtained from a Nyquist theorem equation.
21