Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. We present two novel designs for fixed-point decimal multiplication that utilize decimal carry-save addition to reduce the critical path delay. First, a multiplier that stores a reduced number of multiplicand multiples and uses decimal carry-save addition in the iterative portion of the design is presented. Then, a second multiplier design is proposed with several notable improvements including fast generation of multiplicand multiples that do not need to be stored, the use of decimal (4:2) compressors, and a simplified decimal carry-propagate addition to produce the final product. When multiplying two n-digit operands to produce a 2n-digit product, the improved multiplier design has a worst-case latency of n+4 cycles and an initiation interval of n+1 cycles. Three data-dependent optimizations, which help reduce the multipliers' average latency, are also described. The multipliers presented can be extended to support decimal floating-point multiplication.

Decimal multiplication via carry-save addition

This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD-8421 multiplier operand into minimally redundant signed-digit radix-10, radix-4 and radix-5 representations using new recoders reduces the complexity of partial product generation. In addition, SD radix-4 and radix-5 recodings allow the reuse of a conventional parallel binary radix-4 multiplier to perform combined binary/decimal multiplications. Evaluation results show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and other representative alternatives for decimal multiplication.

/pdf/a-new-family-of-high-performance-parallel-decimal-w9ulvm8r1h.pdf

A New Family of High.Performance Parallel Decimal Multipliers

The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2n-tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix--8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication.

Improved Design of High-Performance Parallel Decimal Multipliers

There is increasing interest in hardware support for decimal arithmetic as a result of recent growth in commercial, financial, and Internet-based applications. Consequently, new specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for floating-point arithmetic. This paper introduces and analyzes three techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Two of the techniques speculate BCD correction values and correct intermediate results while adding the input operands. The first speculates over one addition. The second speculates over two additions. The third technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next more significant digit. Multioperand adder designs are constructed and synthesized for four to 16 input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to several previous techniques for high-speed decimal addition.

/pdf/high-speed-multioperand-decimal-adders-37eiyl046c.pdf

High-speed multioperand decimal adders

With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi- and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations.

http://faculties.sbu.ac.ir/~jaberipur/Papers/Journals/8.pdf

Binary-coded decimal digit multipliers

An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Apparatus for decimal multiplication

In the Internet having a plurality of autonomous systems interconnected, fast routing can be made. The autonomous systems constituting the Internet or the like are divided into groups. The border routers of one group share routing information of the group, and the border routers of another group share routing information of the group. Each border router has a unit for separating a desired one from the autonomous systems of a corresponding group or consolidating an autonomous system of another group into the corresponding group, so that the amount of the routing information held can be adapted to the processing ability of the border routers within that group.

Network structure method and route determination equipment

PROBLEM TO BE SOLVED: To allow the Internet or the like where a plurality of autonomous systems are interconnected to attain high speed routing SOLUTION: Autonomous system groups 10, 20, 30, 40, 50 being components of the Internet or the like are grouped, and border routers 11, 12, 21, 31 of a group 1 and border routers 41, 51 of a group 2 share path information respectively Each border router is provided with a means that separates a desired autonomous system of the group of integrates an autonomous system of other groups in response to traffic and stores path information in matching with a processing capability of the border routers in the group

Network configuration method and path deciding method

Verfahren und vorrichtung zur division von bcd-zahlen

PURPOSE:To obtain a multiplying device which can perform a decimal loop addition at a high speed by using the double input of a 3-input carry save adder as the input of an intermediate product which is shown in the form of a carry and another input as the input of the product of a decimal part. CONSTITUTION:The double input of a 3-input carry save adder is used as the input of an intermediate product shown in the form of a carry, and another input is used as the input of the product of a decimal part. For instance, 6 is added every decimal digit by a 6-addition correcting circuit 28 as the initial setting to start the loop addition. Then the intermediate product held in the form of a sum and a carry is added with the product to a decimal part obtained by another arithmetic means by a 3-input carry save adder CSA29. Then the correction is given to the sum output as well as to an upper decimal digit from a sum output correction circuit 31 and a decimal upper digit corretion circuit 32 for each decimal digit of the CSA29. A decimal addition is carried out for the first intermediate product and the product of a decimal part after the bit positioning is carried out to the sum obtained after a carry correction.

Decimal multiplying device

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