Henry E. Styles
Xilinx
15 Papers
202 Citations
Henry E. Styles is an academic researcher from Xilinx. The author has contributed to research in topics: Reconfigurable computing & Source code. The author has an hindex of 9, co-authored 15 publications.
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Papers
MPI as a Programming Model for High-Performance Reconfigurable Computers
Manuel Saldana,Arun Patel,Christopher A. Madill,Daniel Nunes,Danyao Wang,Paul Chow,Ralph D. Wittig,Henry E. Styles,Andrew Putnam +8 more
TL;DR: TMD-MPI is shown to address current design challenges in HPRC usage, suggesting that the MPI standard has enough syntax and semantics to program these new types of parallel architectures.
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Performance and power of cache-based reconfigurable computing
Andrew Putnam,Susan J. Eggers,Dave Bennett,Eric F. Dellinger,Jeffrey M. Mason,Henry E. Styles,Prasanna Sundararajan,Ralph D. Wittig +7 more
- 20 Jun 2009
TL;DR: The analyses and optimizations of the CHiMPS compiler that construct many-cache caches are presented, showing a performance advantage of 7.8x over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater.
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MPI as an abstraction for software-hardware interaction for HPRCs
Manuel Saldana,Arun Patel,Christopher A. Madill,D. Nunes,Danyao Wang,Henry E. Styles,Andrew Putnam,Ralph D. Wittig,Paul Chow +8 more
- 01 Nov 2008
TL;DR: The evolution and current work on TMD-MPI is presented, which started as an MPI-based programming model for multiprocessor systems-on-chip implemented in FPGAs and has now evolved to include multiple X86 processors.
Performance and power of cache-based reconfigurable computing
Andrew Putnam,Susan J. Eggers,Dave Bennett,Eric F. Dellinger,Jeffrey M. Mason,Henry E. Styles,Prasanna Sundararajan,Ralph D. Wittig +7 more
- 22 Feb 2009
TL;DR: This poster presents the analyses and optimizations of the CHiMPS compiler that construct many-cache caches, and presents the details of the cache parameters on a Xilinx Virtex-5 LX110T FPGA.
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Patent
Heterogeneous multiprocessor program compilation targeting programmable integrated circuits
Henry E. Styles,Jeffrey M. Fifield,Ralph D. Wittig,Philip B. James-Roxby,Santan Sonal,Devadas Varma,Fernando Martinez Vallina,Sheng Zhou,Charles Lo +8 more
- 12 Nov 2014
TL;DR: In this article, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design are presented.
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